06dbbd69f9
Add armclk to the supported clocks on the S3C2440 and S3C2442 to better represent the DVS state which controls whether FCLK or HCLK is fed to the ARM core. Signed-off-by: Ben Dooks <ben-linux@fluff.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
138 lines
3.4 KiB
C
138 lines
3.4 KiB
C
/* linux/arch/arm/plat-s3c24xx/s3c24xx-clock.c
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*
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* Copyright (c) 2004-2005,2008 Simtec Electronics
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* http://armlinux.simtec.co.uk/
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* Ben Dooks <ben@simtec.co.uk>
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*
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* S3C2440/S3C2442 Common clock support
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/list.h>
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#include <linux/errno.h>
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#include <linux/err.h>
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#include <linux/device.h>
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#include <linux/sysdev.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/mutex.h>
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#include <linux/clk.h>
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#include <asm/hardware.h>
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#include <asm/atomic.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/arch/regs-clock.h>
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#include <asm/plat-s3c24xx/clock.h>
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#include <asm/plat-s3c24xx/cpu.h>
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static int s3c2440_setparent_armclk(struct clk *clk, struct clk *parent)
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{
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unsigned long camdivn;
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unsigned long dvs;
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if (parent == &clk_f)
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dvs = 0;
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else if (parent == &clk_h)
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dvs = S3C2440_CAMDIVN_DVSEN;
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else
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return -EINVAL;
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clk->parent = parent;
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camdivn = __raw_readl(S3C2440_CAMDIVN);
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camdivn &= ~S3C2440_CAMDIVN_DVSEN;
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camdivn |= dvs;
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__raw_writel(camdivn, S3C2440_CAMDIVN);
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return 0;
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}
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static struct clk clk_arm = {
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.name = "armclk",
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.id = -1,
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.set_parent = s3c2440_setparent_armclk,
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};
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static int s3c244x_clk_add(struct sys_device *sysdev)
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{
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unsigned long camdivn = __raw_readl(S3C2440_CAMDIVN);
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unsigned long clkdivn;
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struct clk *clock_upll;
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int ret;
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printk("S3C244X: Clock Support, DVS %s\n",
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(camdivn & S3C2440_CAMDIVN_DVSEN) ? "on" : "off");
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clk_arm.parent = (camdivn & S3C2440_CAMDIVN_DVSEN) ? &clk_h : &clk_f;
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ret = s3c24xx_register_clock(&clk_arm);
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if (ret < 0) {
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printk(KERN_ERR "S3C24XX: Failed to add armclk (%d)\n", ret);
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return ret;
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}
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clock_upll = clk_get(NULL, "upll");
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if (IS_ERR(clock_upll)) {
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printk(KERN_ERR "S3C244X: Failed to get upll clock\n");
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return -ENOENT;
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}
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/* check rate of UPLL, and if it is near 96MHz, then change
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* to using half the UPLL rate for the system */
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if (clk_get_rate(clock_upll) > (94 * MHZ)) {
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clk_usb_bus.rate = clk_get_rate(clock_upll) / 2;
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mutex_lock(&clocks_mutex);
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clkdivn = __raw_readl(S3C2410_CLKDIVN);
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clkdivn |= S3C2440_CLKDIVN_UCLK;
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__raw_writel(clkdivn, S3C2410_CLKDIVN);
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mutex_unlock(&clocks_mutex);
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}
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return 0;
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}
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static struct sysdev_driver s3c2440_clk_driver = {
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.add = s3c244x_clk_add,
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};
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static int s3c2440_clk_init(void)
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{
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return sysdev_driver_register(&s3c2440_sysclass, &s3c2440_clk_driver);
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}
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arch_initcall(s3c2440_clk_init);
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static struct sysdev_driver s3c2442_clk_driver = {
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.add = s3c244x_clk_add,
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};
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static int s3c2442_clk_init(void)
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{
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return sysdev_driver_register(&s3c2442_sysclass, &s3c2442_clk_driver);
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}
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arch_initcall(s3c2442_clk_init);
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