078a55fc82
commit 3747069b25e419f6b51395f48127e9812abc3596 upstream.
The __cpuinit type of throwaway sections might have made sense
some time ago when RAM was more constrained, but now the savings
do not offset the cost and complications. For example, the fix in
commit 5e427ec2d0 ("x86: Fix bit corruption at CPU resume time")
is a good example of the nasty type of bugs that can be created
with improper use of the various __init prefixes.
After a discussion on LKML[1] it was decided that cpuinit should go
the way of devinit and be phased out. Once all the users are gone,
we can then finally remove the macros themselves from linux/init.h.
Note that some harmless section mismatch warnings may result, since
notify_cpu_starting() and cpu_up() are arch independent (kernel/cpu.c)
and are flagged as __cpuinit -- so if we remove the __cpuinit from
the arch specific callers, we will also get section mismatch warnings.
As an intermediate step, we intend to turn the linux/init.h cpuinit
related content into no-ops as early as possible, since that will get
rid of these warnings. In any case, they are temporary and harmless.
Here, we remove all the MIPS __cpuinit from C code and __CPUINIT
from asm files. MIPS is interesting in this respect, because there
are also uasm users hiding behind their own renamed versions of the
__cpuinit macros.
[1] https://lkml.org/lkml/2013/5/20/589
[ralf@linux-mips.org: Folded in Paul's followup fix.]
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5494/
Patchwork: https://patchwork.linux-mips.org/patch/5495/
Patchwork: https://patchwork.linux-mips.org/patch/5509/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
108 lines
2.1 KiB
C
108 lines
2.1 KiB
C
/*
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* Copyright (C) 1997, 2001 Ralf Baechle (ralf@gnu.org),
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* derived from r4xx0.c by David S. Miller (davem@davemloft.net).
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <asm/mipsregs.h>
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#include <asm/bcache.h>
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#include <asm/cacheops.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/mmu_context.h>
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#include <asm/r4kcache.h>
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/* Secondary cache size in bytes, if present. */
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static unsigned long scache_size;
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#define SC_LINE 32
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#define SC_PAGE (128*SC_LINE)
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static inline void blast_r5000_scache(void)
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{
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unsigned long start = INDEX_BASE;
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unsigned long end = start + scache_size;
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while(start < end) {
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cache_op(R5K_Page_Invalidate_S, start);
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start += SC_PAGE;
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}
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}
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static void r5k_dma_cache_inv_sc(unsigned long addr, unsigned long size)
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{
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unsigned long end, a;
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/* Catch bad driver code */
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BUG_ON(size == 0);
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if (size >= scache_size) {
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blast_r5000_scache();
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return;
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}
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/* On the R5000 secondary cache we cannot
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* invalidate less than a page at a time.
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* The secondary cache is physically indexed, write-through.
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*/
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a = addr & ~(SC_PAGE - 1);
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end = (addr + size - 1) & ~(SC_PAGE - 1);
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while (a <= end) {
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cache_op(R5K_Page_Invalidate_S, a);
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a += SC_PAGE;
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}
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}
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static void r5k_sc_enable(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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set_c0_config(R5K_CONF_SE);
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blast_r5000_scache();
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local_irq_restore(flags);
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}
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static void r5k_sc_disable(void)
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{
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unsigned long flags;
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local_irq_save(flags);
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blast_r5000_scache();
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clear_c0_config(R5K_CONF_SE);
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local_irq_restore(flags);
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}
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static inline int __init r5k_sc_probe(void)
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{
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unsigned long config = read_c0_config();
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if (config & CONF_SC)
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return(0);
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scache_size = (512 * 1024) << ((config & R5K_CONF_SS) >> 20);
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printk("R5000 SCACHE size %ldkB, linesize 32 bytes.\n",
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scache_size >> 10);
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return 1;
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}
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static struct bcache_ops r5k_sc_ops = {
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.bc_enable = r5k_sc_enable,
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.bc_disable = r5k_sc_disable,
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.bc_wback_inv = r5k_dma_cache_inv_sc,
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.bc_inv = r5k_dma_cache_inv_sc
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};
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void r5k_sc_init(void)
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{
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if (r5k_sc_probe()) {
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r5k_sc_enable();
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bcops = &r5k_sc_ops;
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}
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}
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