38c677cb9a
Patch from David Brownell
ARM genirq cleanups/updates:
- Start switching platforms to newer APIs
* use "irq_chip" name, not "irqchip"
* providing irq_chip.name
- Show irq_chip.name in /proc/interrupts, like on x86.
This update a bit more than half of the ARM code. The irq_chip.name
values were chosen to match docs (if I have them) or be otherwise
obvious ("FPGA", "CPLD", or matching the code).
Signed-off-by: David Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* linux/arch/arm/mach-iop3xx/iop331-irq.c
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*
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* Generic IOP331 IRQ handling functionality
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*
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* Author: Dave Jiang <dave.jiang@intel.com>
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* Copyright (C) 2003 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <asm/mach/irq.h>
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#include <asm/irq.h>
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#include <asm/hardware.h>
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#include <asm/mach-types.h>
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static u32 iop331_mask0 = 0;
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static u32 iop331_mask1 = 0;
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static inline void intctl_write0(u32 val)
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{
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// INTCTL0
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asm volatile("mcr p6,0,%0,c0,c0,0"::"r" (val));
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}
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static inline void intctl_write1(u32 val)
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{
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// INTCTL1
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asm volatile("mcr p6,0,%0,c1,c0,0"::"r" (val));
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}
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static inline void intstr_write0(u32 val)
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{
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// INTSTR0
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asm volatile("mcr p6,0,%0,c2,c0,0"::"r" (val));
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}
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static inline void intstr_write1(u32 val)
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{
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// INTSTR1
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asm volatile("mcr p6,0,%0,c3,c0,0"::"r" (val));
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}
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static void
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iop331_irq_mask1 (unsigned int irq)
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{
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iop331_mask0 &= ~(1 << (irq - IOP331_IRQ_OFS));
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_mask2 (unsigned int irq)
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{
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iop331_mask1 &= ~(1 << (irq - IOP331_IRQ_OFS - 32));
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intctl_write1(iop331_mask1);
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}
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static void
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iop331_irq_unmask1(unsigned int irq)
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{
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iop331_mask0 |= (1 << (irq - IOP331_IRQ_OFS));
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intctl_write0(iop331_mask0);
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}
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static void
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iop331_irq_unmask2(unsigned int irq)
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{
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iop331_mask1 |= (1 << (irq - IOP331_IRQ_OFS - 32));
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intctl_write1(iop331_mask1);
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}
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struct irq_chip iop331_irqchip1 = {
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.name = "IOP-1",
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.ack = iop331_irq_mask1,
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.mask = iop331_irq_mask1,
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.unmask = iop331_irq_unmask1,
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};
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struct irq_chip iop331_irqchip2 = {
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.name = "IOP-2",
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.ack = iop331_irq_mask2,
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.mask = iop331_irq_mask2,
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.unmask = iop331_irq_unmask2,
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};
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void __init iop331_init_irq(void)
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{
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unsigned int i, tmp;
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/* Enable access to coprocessor 6 for dealing with IRQs.
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* From RMK:
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* Basically, the Intel documentation here is poor. It appears that
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* you need to set the bit to be able to access the coprocessor from
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* SVC mode. Whether that allows access from user space or not is
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* unclear.
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*/
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asm volatile (
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"orr %0, %0, %1\n\t"
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"mcr p15, 0, %0, c15, c1, 0\n\t"
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/* The action is delayed, so we have to do this: */
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"mrc p15, 0, %0, c15, c1, 0\n\t"
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"mov %0, %0\n\t"
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"sub pc, pc, #4"
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: "=r" (tmp) : "i" (1 << 6) );
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intctl_write0(0); // disable all interrupts
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intctl_write1(0);
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intstr_write0(0); // treat all as IRQ
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intstr_write1(0);
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if(machine_is_iq80331()) // all interrupts are inputs to chip
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*IOP331_PCIIRSR = 0x0f;
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for(i = IOP331_IRQ_OFS; i < NR_IOP331_IRQS; i++)
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{
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set_irq_chip(i, (i < 32) ? &iop331_irqchip1 : &iop331_irqchip2);
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set_irq_handler(i, do_level_IRQ);
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set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
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}
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}
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