5642530651
The trick is that we do the kernel linear mapping TLB miss starting with an instruction sequence like this: ba,pt %xcc, kvmap_load xor %g2, %g4, %g5 succeeded by an instruction sequence which performs a full page table walk starting at swapper_pg_dir. We first take over the trap table from the firmware. Then, using this constant PTE generation for the linear mapping area above, we build the kernel page tables for the linear mapping. After this is setup, we patch that branch above into a "nop", which will cause TLB misses to fall through to the full page table walk. With this, the page unmapping for CONFIG_DEBUG_PAGEALLOC is trivial. Signed-off-by: David S. Miller <davem@davemloft.net>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
#ifndef _SPARC64_CACHEFLUSH_H
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#define _SPARC64_CACHEFLUSH_H
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#include <linux/config.h>
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#include <asm/page.h>
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#ifndef __ASSEMBLY__
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#include <linux/mm.h>
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/* Cache flush operations. */
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/* These are the same regardless of whether this is an SMP kernel or not. */
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#define flush_cache_mm(__mm) \
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do { if ((__mm) == current->mm) flushw_user(); } while(0)
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#define flush_cache_range(vma, start, end) \
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flush_cache_mm((vma)->vm_mm)
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#define flush_cache_page(vma, page, pfn) \
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flush_cache_mm((vma)->vm_mm)
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/*
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* On spitfire, the icache doesn't snoop local stores and we don't
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* use block commit stores (which invalidate icache lines) during
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* module load, so we need this.
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*/
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extern void flush_icache_range(unsigned long start, unsigned long end);
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extern void __flush_icache_page(unsigned long);
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extern void __flush_dcache_page(void *addr, int flush_icache);
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extern void flush_dcache_page_impl(struct page *page);
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#ifdef CONFIG_SMP
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extern void smp_flush_dcache_page_impl(struct page *page, int cpu);
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extern void flush_dcache_page_all(struct mm_struct *mm, struct page *page);
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#else
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#define smp_flush_dcache_page_impl(page,cpu) flush_dcache_page_impl(page)
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#define flush_dcache_page_all(mm,page) flush_dcache_page_impl(page)
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#endif
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extern void __flush_dcache_range(unsigned long start, unsigned long end);
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extern void flush_dcache_page(struct page *page);
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#define flush_icache_page(vma, pg) do { } while(0)
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#define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
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extern void flush_ptrace_access(struct vm_area_struct *, struct page *,
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unsigned long uaddr, void *kaddr,
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unsigned long len, int write);
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#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page)); \
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memcpy(dst, src, len); \
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flush_ptrace_access(vma, page, vaddr, src, len, 0); \
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} while (0)
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#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
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do { \
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flush_cache_page(vma, vaddr, page_to_pfn(page)); \
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memcpy(dst, src, len); \
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flush_ptrace_access(vma, page, vaddr, dst, len, 1); \
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} while (0)
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#define flush_dcache_mmap_lock(mapping) do { } while (0)
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#define flush_dcache_mmap_unlock(mapping) do { } while (0)
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#define flush_cache_vmap(start, end) do { } while (0)
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#define flush_cache_vunmap(start, end) do { } while (0)
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#ifdef CONFIG_DEBUG_PAGEALLOC
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/* internal debugging function */
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void kernel_map_pages(struct page *page, int numpages, int enable);
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#endif
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#endif /* !__ASSEMBLY__ */
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#endif /* _SPARC64_CACHEFLUSH_H */
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