7175f80ba3
Commit6f6f6a7"ARM: create a common IOMEM definition" moved macro IOMEM(), and requires users to include <asm/assembler.h>. Fix Tegra's sleep.S to do so. This fixes: arch/arm/mach-tegra/sleep.S: Assembler messages: arch/arm/mach-tegra/sleep.S:77: Error: missing ')' arch/arm/mach-tegra/sleep.S:77: Error: garbage following instruction -- `movw r0,#:lower16:(0x60007000-0x60000000+IOMEM(0xFE200000))' Note: This only shows up after0a25893"ARM: tegra: update defconfig" Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
94 lines
2.5 KiB
ArmAsm
94 lines
2.5 KiB
ArmAsm
/*
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* arch/arm/mach-tegra/sleep.S
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*
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* Copyright (c) 2010-2011, NVIDIA Corporation.
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* Copyright (c) 2011, Google, Inc.
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*
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* Author: Colin Cross <ccross@android.com>
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* Gary King <gking@nvidia.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/linkage.h>
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#include <asm/assembler.h>
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#include <mach/iomap.h>
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#include "flowctrl.h"
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#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
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+ IO_PPSB_VIRT)
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/* returns the offset of the flow controller halt register for a cpu */
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.macro cpu_to_halt_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x14
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moveq \rd, #0
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.endm
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/* returns the offset of the flow controller csr register for a cpu */
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.macro cpu_to_csr_reg rd, rcpu
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cmp \rcpu, #0
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subne \rd, \rcpu, #1
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movne \rd, \rd, lsl #3
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addne \rd, \rd, #0x18
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moveq \rd, #8
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.endm
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/* returns the ID of the current processor */
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.macro cpu_id, rd
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mrc p15, 0, \rd, c0, c0, 5
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and \rd, \rd, #0xF
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.endm
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/* loads a 32-bit value into a register without a data access */
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.macro mov32, reg, val
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movw \reg, #:lower16:\val
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movt \reg, #:upper16:\val
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.endm
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/*
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* tegra_cpu_wfi
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*
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* puts current CPU in clock-gated wfi using the flow controller
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*
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* corrupts r0-r3
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* must be called with MMU on
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*/
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ENTRY(tegra_cpu_wfi)
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cpu_id r0
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cpu_to_halt_reg r1, r0
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cpu_to_csr_reg r2, r0
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mov32 r0, TEGRA_FLOW_CTRL_VIRT
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mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
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str r3, [r0, r2] @ clear event & interrupt status
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mov r3, #FLOW_CTRL_WAIT_FOR_INTERRUPT | FLOW_CTRL_JTAG_RESUME
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str r3, [r0, r1] @ put flow controller in wait irq mode
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dsb
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wfi
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mov r3, #0
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str r3, [r0, r1] @ clear flow controller halt status
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mov r3, #FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG
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str r3, [r0, r2] @ clear event & interrupt status
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dsb
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mov pc, lr
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ENDPROC(tegra_cpu_wfi)
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