8fc8598e61
Add Realtek linux driver for rtl8192u as provided by Realtek rtl8192u_linux_2.6.0006.1031.2008.tar.gz, send to me C/C staging ML. This version won't compile against upstream, doesn't follow Linux CodingStyle and has their own ieee80211 stack. Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
313 lines
10 KiB
C
313 lines
10 KiB
C
/*
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This is part of the rtl8192 driver
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released under the GPL (See file COPYING for details).
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This files contains programming code for the rtl8256
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radio frontend.
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*Many* thanks to Realtek Corp. for their great support!
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*/
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#include "r8192U.h"
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#include "r8192U_hw.h"
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#include "r819xU_phyreg.h"
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#include "r819xU_phy.h"
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#include "r8190_rtl8256.h"
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/*--------------------------------------------------------------------------
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* Overview: set RF band width (20M or 40M)
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* Input: struct net_device* dev
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* WIRELESS_BANDWIDTH_E Bandwidth //20M or 40M
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* Output: NONE
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* Return: NONE
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* Note: 8226 support both 20M and 40 MHz
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*---------------------------------------------------------------------------*/
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void PHY_SetRF8256Bandwidth(struct net_device* dev , HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
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{
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u8 eRFPath;
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struct r8192_priv *priv = ieee80211_priv(dev);
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//for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
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for(eRFPath = 0; eRFPath <RF90_PATH_MAX; eRFPath++)
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{
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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continue;
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switch(Bandwidth)
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{
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case HT_CHANNEL_WIDTH_20:
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if(priv->card_8192_version == VERSION_819xU_A || priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
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{
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x100); //phy para:1ba
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3d7);
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x021);
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//cosa add for sd3's request 01/23/2008
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
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}
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else
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{
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RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
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}
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break;
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case HT_CHANNEL_WIDTH_20_40:
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if(priv->card_8192_version == VERSION_819xU_A ||priv->card_8192_version == VERSION_819xU_B)// 8256 D-cut, E-cut, xiong: consider it later!
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{
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0b, bMask12Bits, 0x300); //phy para:3ba
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x2c, bMask12Bits, 0x3df);
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x0e, bMask12Bits, 0x0a1);
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//cosa add for sd3's request 01/23/2008
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if(priv->chan == 3 || priv->chan == 9) //I need to set priv->chan whenever current channel changes
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x59b);
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else
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, 0x14, bMask12Bits, 0x5ab);
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}
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else
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{
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RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown hardware version\n");
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}
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break;
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default:
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RT_TRACE(COMP_ERR, "PHY_SetRF8256Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth );
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break;
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}
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}
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return;
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}
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/*--------------------------------------------------------------------------
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* Overview: Interface to config 8256
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* Input: struct net_device* dev
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* Output: NONE
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* Return: NONE
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*---------------------------------------------------------------------------*/
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void PHY_RF8256_Config(struct net_device* dev)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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// Initialize general global value
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//
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// TODO: Extend RF_PATH_C and RF_PATH_D in the future
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priv->NumTotalRFPath = RTL819X_TOTAL_RF_PATH;
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// Config BB and RF
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phy_RF8256_Config_ParaFile(dev);
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return;
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}
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/*--------------------------------------------------------------------------
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* Overview: Interface to config 8256
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* Input: struct net_device* dev
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* Output: NONE
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* Return: NONE
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*---------------------------------------------------------------------------*/
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void phy_RF8256_Config_ParaFile(struct net_device* dev)
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{
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u32 u4RegValue = 0;
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//static s1Byte szRadioAFile[] = RTL819X_PHY_RADIO_A;
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//static s1Byte szRadioBFile[] = RTL819X_PHY_RADIO_B;
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//static s1Byte szRadioCFile[] = RTL819X_PHY_RADIO_C;
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//static s1Byte szRadioDFile[] = RTL819X_PHY_RADIO_D;
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u8 eRFPath;
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BB_REGISTER_DEFINITION_T *pPhyReg;
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struct r8192_priv *priv = ieee80211_priv(dev);
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u32 RegOffSetToBeCheck = 0x3;
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u32 RegValueToBeCheck = 0x7f1;
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u32 RF3_Final_Value = 0;
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u8 ConstRetryTimes = 5, RetryTimes = 5;
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u8 ret = 0;
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//3//-----------------------------------------------------------------
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//3// <2> Initialize RF
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//3//-----------------------------------------------------------------
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for(eRFPath = (RF90_RADIO_PATH_E)RF90_PATH_A; eRFPath <priv->NumTotalRFPath; eRFPath++)
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{
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if (!rtl8192_phy_CheckIsLegalRFPath(dev, eRFPath))
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continue;
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pPhyReg = &priv->PHYRegDef[eRFPath];
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// Joseph test for shorten RF config
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// pHalData->RfReg0Value[eRFPath] = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, rGlobalCtrl, bMaskDWord);
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/*----Store original RFENV control type----*/
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switch(eRFPath)
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{
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case RF90_PATH_A:
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case RF90_PATH_C:
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u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
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break;
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case RF90_PATH_B :
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case RF90_PATH_D:
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u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
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break;
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}
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/*----Set RF_ENV enable----*/
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rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
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/*----Set RF_ENV output high----*/
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rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
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/* Set bit number of Address and Data for RF register */
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0); // Set 0 to 4 bits for Z-serial and set 1 to 6 bits for 8258
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rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0); // Set 0 to 12 bits for Z-serial and 8258, and set 1 to 14 bits for ???
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rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E) eRFPath, 0x0, bMask12Bits, 0xbf);
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/*----Check RF block (for FPGA platform only)----*/
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// TODO: this function should be removed on ASIC , Emily 2007.2.2
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if (rtl8192_phy_checkBBAndRF(dev, HW90_BLOCK_RF, (RF90_RADIO_PATH_E)eRFPath))
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{
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RT_TRACE(COMP_ERR, "PHY_RF8256_Config():Check Radio[%d] Fail!!\n", eRFPath);
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goto phy_RF8256_Config_ParaFile_Fail;
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}
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RetryTimes = ConstRetryTimes;
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RF3_Final_Value = 0;
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/*----Initialize RF fom connfiguration file----*/
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switch(eRFPath)
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{
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case RF90_PATH_A:
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while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
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{
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ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
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RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
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RetryTimes--;
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}
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break;
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case RF90_PATH_B:
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while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
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{
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ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
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RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
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RetryTimes--;
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}
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break;
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case RF90_PATH_C:
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while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
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{
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ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
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RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
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RetryTimes--;
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}
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break;
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case RF90_PATH_D:
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while(RF3_Final_Value!=RegValueToBeCheck && RetryTimes!=0)
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{
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ret = rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
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RF3_Final_Value = rtl8192_phy_QueryRFReg(dev, (RF90_RADIO_PATH_E)eRFPath, RegOffSetToBeCheck, bMask12Bits);
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RT_TRACE(COMP_RF, "RF %d %d register final value: %x\n", eRFPath, RegOffSetToBeCheck, RF3_Final_Value);
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RetryTimes--;
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}
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break;
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}
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/*----Restore RFENV control type----*/;
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switch(eRFPath)
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{
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case RF90_PATH_A:
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case RF90_PATH_C:
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rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
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break;
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case RF90_PATH_B :
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case RF90_PATH_D:
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rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
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break;
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}
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if(ret){
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RT_TRACE(COMP_ERR, "phy_RF8256_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
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goto phy_RF8256_Config_ParaFile_Fail;
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}
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}
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RT_TRACE(COMP_PHY, "PHY Initialization Success\n") ;
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return ;
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phy_RF8256_Config_ParaFile_Fail:
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RT_TRACE(COMP_ERR, "PHY Initialization failed\n") ;
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return ;
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}
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void PHY_SetRF8256CCKTxPower(struct net_device* dev, u8 powerlevel)
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{
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u32 TxAGC=0;
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struct r8192_priv *priv = ieee80211_priv(dev);
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//modified by vivi, 20080109
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TxAGC = powerlevel;
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if(priv->bDynamicTxLowPower == TRUE ) //cosa 05/22/2008 for scan
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{
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if(priv->CustomerID == RT_CID_819x_Netcore)
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TxAGC = 0x22;
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else
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TxAGC += priv->CckPwEnl;
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}
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if(TxAGC > 0x24)
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TxAGC = 0x24;
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rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
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}
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void PHY_SetRF8256OFDMTxPower(struct net_device* dev, u8 powerlevel)
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{
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struct r8192_priv *priv = ieee80211_priv(dev);
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//Joseph TxPower for 8192 testing
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u32 writeVal, powerBase0, powerBase1, writeVal_tmp;
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u8 index = 0;
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u16 RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
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u8 byte0, byte1, byte2, byte3;
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powerBase0 = powerlevel + priv->TxPowerDiff; //OFDM rates
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powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
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powerBase1 = powerlevel; //MCS rates
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powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
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for(index=0; index<6; index++)
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{
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writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
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byte0 = (u8)(writeVal & 0x7f);
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byte1 = (u8)((writeVal & 0x7f00)>>8);
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byte2 = (u8)((writeVal & 0x7f0000)>>16);
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byte3 = (u8)((writeVal & 0x7f000000)>>24);
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if(byte0 > 0x24) // Max power index = 0x24
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byte0 = 0x24;
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if(byte1 > 0x24)
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byte1 = 0x24;
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if(byte2 > 0x24)
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byte2 = 0x24;
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if(byte3 > 0x24)
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byte3 = 0x24;
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//for tx power track
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if(index == 3)
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{
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writeVal_tmp = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
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priv->Pwr_Track = writeVal_tmp;
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}
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if(priv->bDynamicTxHighPower == TRUE) //Add by Jacken 2008/03/06
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{
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// Emily, 20080613. Set low tx power for both MCS and legacy OFDM
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writeVal = 0x03030303;
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}
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else
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{
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writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
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}
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rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
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}
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return;
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}
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