1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
571 lines
19 KiB
C
571 lines
19 KiB
C
#ifndef _LMC_VAR_H_
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#define _LMC_VAR_H_
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/* $Id: lmc_var.h,v 1.17 2000/04/06 12:16:47 asj Exp $ */
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/*
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* Copyright (c) 1997-2000 LAN Media Corporation (LMC)
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* All rights reserved. www.lanmedia.com
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*
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* This code is written by:
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* Andrew Stanley-Jones (asj@cban.com)
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* Rob Braun (bbraun@vix.com),
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* Michael Graff (explorer@vix.com) and
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* Matt Thomas (matt@3am-software.com).
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License version 2, incorporated herein by reference.
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*/
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#include <linux/timer.h>
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#ifndef __KERNEL__
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typedef signed char s8;
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typedef unsigned char u8;
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typedef signed short s16;
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typedef unsigned short u16;
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typedef signed int s32;
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typedef unsigned int u32;
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typedef signed long long s64;
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typedef unsigned long long u64;
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#define BITS_PER_LONG 32
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#endif
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/*
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* basic definitions used in lmc include files
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*/
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typedef struct lmc___softc lmc_softc_t;
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typedef struct lmc___media lmc_media_t;
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typedef struct lmc___ctl lmc_ctl_t;
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#define lmc_csrptr_t unsigned long
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#define u_int16_t u16
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#define u_int8_t u8
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#define tulip_uint32_t u32
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#define LMC_REG_RANGE 0x80
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#define LMC_PRINTF_FMT "%s"
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#define LMC_PRINTF_ARGS (sc->lmc_device->name)
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#define TX_TIMEOUT (2*HZ)
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#define LMC_TXDESCS 32
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#define LMC_RXDESCS 32
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#define LMC_LINK_UP 1
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#define LMC_LINK_DOWN 0
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/* These macros for generic read and write to and from the dec chip */
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#define LMC_CSR_READ(sc, csr) \
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inl((sc)->lmc_csrs.csr)
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#define LMC_CSR_WRITE(sc, reg, val) \
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outl((val), (sc)->lmc_csrs.reg)
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//#ifdef _LINUX_DELAY_H
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// #define SLOW_DOWN_IO udelay(2);
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// #undef __SLOW_DOWN_IO
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// #define __SLOW_DOWN_IO udelay(2);
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//#endif
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#define DELAY(n) SLOW_DOWN_IO
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#define lmc_delay() inl(sc->lmc_csrs.csr_9)
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/* This macro sync's up with the mii so that reads and writes can take place */
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#define LMC_MII_SYNC(sc) do {int n=32; while( n >= 0 ) { \
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LMC_CSR_WRITE((sc), csr_9, 0x20000); \
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lmc_delay(); \
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LMC_CSR_WRITE((sc), csr_9, 0x30000); \
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lmc_delay(); \
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n--; }} while(0)
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struct lmc_regfile_t {
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lmc_csrptr_t csr_busmode; /* CSR0 */
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lmc_csrptr_t csr_txpoll; /* CSR1 */
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lmc_csrptr_t csr_rxpoll; /* CSR2 */
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lmc_csrptr_t csr_rxlist; /* CSR3 */
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lmc_csrptr_t csr_txlist; /* CSR4 */
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lmc_csrptr_t csr_status; /* CSR5 */
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lmc_csrptr_t csr_command; /* CSR6 */
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lmc_csrptr_t csr_intr; /* CSR7 */
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lmc_csrptr_t csr_missed_frames; /* CSR8 */
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lmc_csrptr_t csr_9; /* CSR9 */
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lmc_csrptr_t csr_10; /* CSR10 */
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lmc_csrptr_t csr_11; /* CSR11 */
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lmc_csrptr_t csr_12; /* CSR12 */
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lmc_csrptr_t csr_13; /* CSR13 */
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lmc_csrptr_t csr_14; /* CSR14 */
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lmc_csrptr_t csr_15; /* CSR15 */
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};
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#define csr_enetrom csr_9 /* 21040 */
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#define csr_reserved csr_10 /* 21040 */
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#define csr_full_duplex csr_11 /* 21040 */
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#define csr_bootrom csr_10 /* 21041/21140A/?? */
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#define csr_gp csr_12 /* 21140* */
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#define csr_watchdog csr_15 /* 21140* */
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#define csr_gp_timer csr_11 /* 21041/21140* */
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#define csr_srom_mii csr_9 /* 21041/21140* */
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#define csr_sia_status csr_12 /* 2104x */
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#define csr_sia_connectivity csr_13 /* 2104x */
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#define csr_sia_tx_rx csr_14 /* 2104x */
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#define csr_sia_general csr_15 /* 2104x */
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/* tulip length/control transmit descriptor definitions
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* used to define bits in the second tulip_desc_t field (length)
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* for the transmit descriptor -baz */
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#define LMC_TDES_FIRST_BUFFER_SIZE ((u_int32_t)(0x000007FF))
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#define LMC_TDES_SECOND_BUFFER_SIZE ((u_int32_t)(0x003FF800))
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#define LMC_TDES_HASH_FILTERING ((u_int32_t)(0x00400000))
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#define LMC_TDES_DISABLE_PADDING ((u_int32_t)(0x00800000))
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#define LMC_TDES_SECOND_ADDR_CHAINED ((u_int32_t)(0x01000000))
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#define LMC_TDES_END_OF_RING ((u_int32_t)(0x02000000))
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#define LMC_TDES_ADD_CRC_DISABLE ((u_int32_t)(0x04000000))
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#define LMC_TDES_SETUP_PACKET ((u_int32_t)(0x08000000))
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#define LMC_TDES_INVERSE_FILTERING ((u_int32_t)(0x10000000))
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#define LMC_TDES_FIRST_SEGMENT ((u_int32_t)(0x20000000))
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#define LMC_TDES_LAST_SEGMENT ((u_int32_t)(0x40000000))
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#define LMC_TDES_INTERRUPT_ON_COMPLETION ((u_int32_t)(0x80000000))
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#define TDES_SECOND_BUFFER_SIZE_BIT_NUMBER 11
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#define TDES_COLLISION_COUNT_BIT_NUMBER 3
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/* Constants for the RCV descriptor RDES */
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#define LMC_RDES_OVERFLOW ((u_int32_t)(0x00000001))
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#define LMC_RDES_CRC_ERROR ((u_int32_t)(0x00000002))
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#define LMC_RDES_DRIBBLING_BIT ((u_int32_t)(0x00000004))
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#define LMC_RDES_REPORT_ON_MII_ERR ((u_int32_t)(0x00000008))
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#define LMC_RDES_RCV_WATCHDOG_TIMEOUT ((u_int32_t)(0x00000010))
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#define LMC_RDES_FRAME_TYPE ((u_int32_t)(0x00000020))
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#define LMC_RDES_COLLISION_SEEN ((u_int32_t)(0x00000040))
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#define LMC_RDES_FRAME_TOO_LONG ((u_int32_t)(0x00000080))
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#define LMC_RDES_LAST_DESCRIPTOR ((u_int32_t)(0x00000100))
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#define LMC_RDES_FIRST_DESCRIPTOR ((u_int32_t)(0x00000200))
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#define LMC_RDES_MULTICAST_FRAME ((u_int32_t)(0x00000400))
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#define LMC_RDES_RUNT_FRAME ((u_int32_t)(0x00000800))
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#define LMC_RDES_DATA_TYPE ((u_int32_t)(0x00003000))
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#define LMC_RDES_LENGTH_ERROR ((u_int32_t)(0x00004000))
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#define LMC_RDES_ERROR_SUMMARY ((u_int32_t)(0x00008000))
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#define LMC_RDES_FRAME_LENGTH ((u_int32_t)(0x3FFF0000))
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#define LMC_RDES_OWN_BIT ((u_int32_t)(0x80000000))
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#define RDES_FRAME_LENGTH_BIT_NUMBER 16
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#define LMC_RDES_ERROR_MASK ( (u_int32_t)( \
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LMC_RDES_OVERFLOW \
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| LMC_RDES_DRIBBLING_BIT \
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| LMC_RDES_REPORT_ON_MII_ERR \
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| LMC_RDES_COLLISION_SEEN ) )
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/*
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* Ioctl info
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*/
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typedef struct {
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u_int32_t n;
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u_int32_t m;
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u_int32_t v;
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u_int32_t x;
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u_int32_t r;
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u_int32_t f;
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u_int32_t exact;
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} lmc_av9110_t;
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/*
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* Common structure passed to the ioctl code.
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*/
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struct lmc___ctl {
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u_int32_t cardtype;
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u_int32_t clock_source; /* HSSI, T1 */
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u_int32_t clock_rate; /* T1 */
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u_int32_t crc_length;
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u_int32_t cable_length; /* DS3 */
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u_int32_t scrambler_onoff; /* DS3 */
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u_int32_t cable_type; /* T1 */
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u_int32_t keepalive_onoff; /* protocol */
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u_int32_t ticks; /* ticks/sec */
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union {
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lmc_av9110_t ssi;
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} cardspec;
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u_int32_t circuit_type; /* T1 or E1 */
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};
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/*
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* Carefull, look at the data sheet, there's more to this
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* structure than meets the eye. It should probably be:
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*
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* struct tulip_desc_t {
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* u8 own:1;
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* u32 status:31;
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* u32 control:10;
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* u32 buffer1;
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* u32 buffer2;
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* };
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* You could also expand status control to provide more bit information
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*/
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struct tulip_desc_t {
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s32 status;
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s32 length;
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u32 buffer1;
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u32 buffer2;
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};
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/*
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* media independent methods to check on media status, link, light LEDs,
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* etc.
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*/
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struct lmc___media {
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void (* init)(lmc_softc_t * const);
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void (* defaults)(lmc_softc_t * const);
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void (* set_status)(lmc_softc_t * const, lmc_ctl_t *);
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void (* set_clock_source)(lmc_softc_t * const, int);
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void (* set_speed)(lmc_softc_t * const, lmc_ctl_t *);
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void (* set_cable_length)(lmc_softc_t * const, int);
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void (* set_scrambler)(lmc_softc_t * const, int);
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int (* get_link_status)(lmc_softc_t * const);
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void (* set_link_status)(lmc_softc_t * const, int);
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void (* set_crc_length)(lmc_softc_t * const, int);
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void (* set_circuit_type)(lmc_softc_t * const, int);
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void (* watchdog)(lmc_softc_t * const);
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};
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#define STATCHECK 0xBEEFCAFE
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/* Included in this structure are first
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* - standard net_device_stats
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* - some other counters used for debug and driver performance
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* evaluation -baz
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*/
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struct lmc_statistics
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{
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unsigned long rx_packets; /* total packets received */
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unsigned long tx_packets; /* total packets transmitted */
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unsigned long rx_bytes;
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unsigned long tx_bytes;
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unsigned long rx_errors; /* bad packets received */
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unsigned long tx_errors; /* packet transmit problems */
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unsigned long rx_dropped; /* no space in linux buffers */
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unsigned long tx_dropped; /* no space available in linux */
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unsigned long multicast; /* multicast packets received */
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unsigned long collisions;
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/* detailed rx_errors: */
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unsigned long rx_length_errors;
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unsigned long rx_over_errors; /* receiver ring buff overflow */
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unsigned long rx_crc_errors; /* recved pkt with crc error */
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unsigned long rx_frame_errors; /* recv'd frame alignment error */
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unsigned long rx_fifo_errors; /* recv'r fifo overrun */
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unsigned long rx_missed_errors; /* receiver missed packet */
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/* detailed tx_errors */
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unsigned long tx_aborted_errors;
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unsigned long tx_carrier_errors;
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unsigned long tx_fifo_errors;
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unsigned long tx_heartbeat_errors;
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unsigned long tx_window_errors;
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/* for cslip etc */
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unsigned long rx_compressed;
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unsigned long tx_compressed;
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/* -------------------------------------
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* Custom stats & counters follow -baz */
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u_int32_t version_size;
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u_int32_t lmc_cardtype;
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u_int32_t tx_ProcTimeout;
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u_int32_t tx_IntTimeout;
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u_int32_t tx_NoCompleteCnt;
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u_int32_t tx_MaxXmtsB4Int;
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u_int32_t tx_TimeoutCnt;
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u_int32_t tx_OutOfSyncPtr;
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u_int32_t tx_tbusy0;
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u_int32_t tx_tbusy1;
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u_int32_t tx_tbusy_calls;
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u_int32_t resetCount;
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u_int32_t lmc_txfull;
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u_int32_t tbusy;
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u_int32_t dirtyTx;
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u_int32_t lmc_next_tx;
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u_int32_t otherTypeCnt;
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u_int32_t lastType;
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u_int32_t lastTypeOK;
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u_int32_t txLoopCnt;
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u_int32_t usedXmtDescripCnt;
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u_int32_t txIndexCnt;
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u_int32_t rxIntLoopCnt;
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u_int32_t rx_SmallPktCnt;
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u_int32_t rx_BadPktSurgeCnt;
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u_int32_t rx_BuffAllocErr;
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u_int32_t tx_lossOfClockCnt;
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/* T1 error counters */
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u_int32_t framingBitErrorCount;
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u_int32_t lineCodeViolationCount;
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u_int32_t lossOfFrameCount;
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u_int32_t changeOfFrameAlignmentCount;
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u_int32_t severelyErroredFrameCount;
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u_int32_t check;
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};
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typedef struct lmc_xinfo {
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u_int32_t Magic0; /* BEEFCAFE */
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u_int32_t PciCardType;
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u_int32_t PciSlotNumber; /* PCI slot number */
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u_int16_t DriverMajorVersion;
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u_int16_t DriverMinorVersion;
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u_int16_t DriverSubVersion;
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u_int16_t XilinxRevisionNumber;
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u_int16_t MaxFrameSize;
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u_int16_t t1_alarm1_status;
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u_int16_t t1_alarm2_status;
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int link_status;
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u_int32_t mii_reg16;
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u_int32_t Magic1; /* DEADBEEF */
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} LMC_XINFO;
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/*
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* forward decl
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*/
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struct lmc___softc {
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void *if_ptr; /* General purpose pointer (used by SPPP) */
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char *name;
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u8 board_idx;
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struct lmc_statistics stats;
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struct net_device *lmc_device;
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int hang, rxdesc, bad_packet, some_counter;
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u_int32_t txgo;
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struct lmc_regfile_t lmc_csrs;
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volatile u_int32_t lmc_txtick;
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volatile u_int32_t lmc_rxtick;
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u_int32_t lmc_flags;
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u_int32_t lmc_intrmask; /* our copy of csr_intr */
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u_int32_t lmc_cmdmode; /* our copy of csr_cmdmode */
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u_int32_t lmc_busmode; /* our copy of csr_busmode */
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u_int32_t lmc_gpio_io; /* state of in/out settings */
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u_int32_t lmc_gpio; /* state of outputs */
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struct sk_buff* lmc_txq[LMC_TXDESCS];
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struct sk_buff* lmc_rxq[LMC_RXDESCS];
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volatile
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struct tulip_desc_t lmc_rxring[LMC_RXDESCS];
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volatile
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struct tulip_desc_t lmc_txring[LMC_TXDESCS];
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unsigned int lmc_next_rx, lmc_next_tx;
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volatile
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unsigned int lmc_taint_tx, lmc_taint_rx;
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int lmc_tx_start, lmc_txfull;
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int lmc_txbusy;
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u_int16_t lmc_miireg16;
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int lmc_ok;
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int last_link_status;
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int lmc_cardtype;
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u_int32_t last_frameerr;
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lmc_media_t *lmc_media;
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struct timer_list timer;
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lmc_ctl_t ictl;
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u_int32_t TxDescriptControlInit;
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int tx_TimeoutInd; /* additional driver state */
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int tx_TimeoutDisplay;
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unsigned int lastlmc_taint_tx;
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int lasttx_packets;
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u_int32_t tx_clockState;
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u_int32_t lmc_crcSize;
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LMC_XINFO lmc_xinfo;
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char lmc_yel, lmc_blue, lmc_red; /* for T1 and DS3 */
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char lmc_timing; /* for HSSI and SSI */
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int got_irq;
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char last_led_err[4];
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u32 last_int;
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u32 num_int;
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spinlock_t lmc_lock;
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u_int16_t if_type; /* PPP or NET */
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struct ppp_device *pd;
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/* Failure cases */
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u8 failed_ring;
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u8 failed_recv_alloc;
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/* Structure check */
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u32 check;
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};
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#define LMC_PCI_TIME 1
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#define LMC_EXT_TIME 0
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#define PKT_BUF_SZ 1542 /* was 1536 */
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/* CSR5 settings */
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#define TIMER_INT 0x00000800
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#define TP_LINK_FAIL 0x00001000
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#define TP_LINK_PASS 0x00000010
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#define NORMAL_INT 0x00010000
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#define ABNORMAL_INT 0x00008000
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#define RX_JABBER_INT 0x00000200
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#define RX_DIED 0x00000100
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#define RX_NOBUFF 0x00000080
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#define RX_INT 0x00000040
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#define TX_FIFO_UNDER 0x00000020
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#define TX_JABBER 0x00000008
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#define TX_NOBUFF 0x00000004
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#define TX_DIED 0x00000002
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#define TX_INT 0x00000001
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/* CSR6 settings */
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#define OPERATION_MODE 0x00000200 /* Full Duplex */
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#define PROMISC_MODE 0x00000040 /* Promiscuous Mode */
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#define RECIEVE_ALL 0x40000000 /* Recieve All */
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#define PASS_BAD_FRAMES 0x00000008 /* Pass Bad Frames */
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/* Dec control registers CSR6 as well */
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#define LMC_DEC_ST 0x00002000
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#define LMC_DEC_SR 0x00000002
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/* CSR15 settings */
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#define RECV_WATCHDOG_DISABLE 0x00000010
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#define JABBER_DISABLE 0x00000001
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/* More settings */
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/*
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* aSR6 -- Command (Operation Mode) Register
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*/
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#define TULIP_CMD_RECEIVEALL 0x40000000L /* (RW) Receivel all frames? */
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#define TULIP_CMD_MUSTBEONE 0x02000000L /* (RW) Must Be One (21140) */
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#define TULIP_CMD_TXTHRSHLDCTL 0x00400000L /* (RW) Transmit Threshold Mode (21140) */
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#define TULIP_CMD_STOREFWD 0x00200000L /* (RW) Store and Foward (21140) */
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#define TULIP_CMD_NOHEARTBEAT 0x00080000L /* (RW) No Heartbeat (21140) */
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#define TULIP_CMD_PORTSELECT 0x00040000L /* (RW) Post Select (100Mb) (21140) */
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#define TULIP_CMD_FULLDUPLEX 0x00000200L /* (RW) Full Duplex Mode */
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#define TULIP_CMD_OPERMODE 0x00000C00L /* (RW) Operating Mode */
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#define TULIP_CMD_PROMISCUOUS 0x00000041L /* (RW) Promiscuous Mode */
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#define TULIP_CMD_PASSBADPKT 0x00000008L /* (RW) Pass Bad Frames */
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#define TULIP_CMD_THRESHOLDCTL 0x0000C000L /* (RW) Threshold Control */
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#define TULIP_GP_PINSET 0x00000100L
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#define TULIP_BUSMODE_SWRESET 0x00000001L
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#define TULIP_WATCHDOG_TXDISABLE 0x00000001L
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#define TULIP_WATCHDOG_RXDISABLE 0x00000010L
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#define TULIP_STS_NORMALINTR 0x00010000L /* (RW) Normal Interrupt */
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#define TULIP_STS_ABNRMLINTR 0x00008000L /* (RW) Abnormal Interrupt */
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#define TULIP_STS_ERI 0x00004000L /* (RW) Early Receive Interrupt */
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#define TULIP_STS_SYSERROR 0x00002000L /* (RW) System Error */
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#define TULIP_STS_GTE 0x00000800L /* (RW) General Pupose Timer Exp */
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#define TULIP_STS_ETI 0x00000400L /* (RW) Early Transmit Interrupt */
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#define TULIP_STS_RXWT 0x00000200L /* (RW) Receiver Watchdog Timeout */
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#define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receiver Process Stopped */
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#define TULIP_STS_RXNOBUF 0x00000080L /* (RW) Receive Buf Unavail */
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#define TULIP_STS_RXINTR 0x00000040L /* (RW) Receive Interrupt */
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#define TULIP_STS_TXUNDERFLOW 0x00000020L /* (RW) Transmit Underflow */
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#define TULIP_STS_TXJABER 0x00000008L /* (RW) Jabber timeout */
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#define TULIP_STS_TXNOBUF 0x00000004L
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#define TULIP_STS_TXSTOPPED 0x00000002L /* (RW) Transmit Process Stopped */
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#define TULIP_STS_TXINTR 0x00000001L /* (RW) Transmit Interrupt */
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#define TULIP_STS_RXS_STOPPED 0x00000000L /* 000 - Stopped */
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#define TULIP_STS_RXSTOPPED 0x00000100L /* (RW) Receive Process Stopped */
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#define TULIP_STS_RXNOBUF 0x00000080L
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#define TULIP_CMD_TXRUN 0x00002000L /* (RW) Start/Stop Transmitter */
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#define TULIP_CMD_RXRUN 0x00000002L /* (RW) Start/Stop Receive Filtering */
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#define TULIP_DSTS_TxDEFERRED 0x00000001 /* Initially Deferred */
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#define TULIP_DSTS_OWNER 0x80000000 /* Owner (1 = 21040) */
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#define TULIP_DSTS_RxMIIERR 0x00000008
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#define LMC_DSTS_ERRSUM (TULIP_DSTS_RxMIIERR)
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#define TULIP_DEFAULT_INTR_MASK (TULIP_STS_NORMALINTR \
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| TULIP_STS_RXINTR \
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| TULIP_STS_TXINTR \
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| TULIP_STS_ABNRMLINTR \
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| TULIP_STS_SYSERROR \
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| TULIP_STS_TXSTOPPED \
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| TULIP_STS_TXUNDERFLOW\
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| TULIP_STS_RXSTOPPED )
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#define DESC_OWNED_BY_SYSTEM ((u_int32_t)(0x00000000))
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#define DESC_OWNED_BY_DC21X4 ((u_int32_t)(0x80000000))
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#ifndef TULIP_CMD_RECEIVEALL
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#define TULIP_CMD_RECEIVEALL 0x40000000L
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#endif
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/* Adapter module number */
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#define LMC_ADAP_HSSI 2
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#define LMC_ADAP_DS3 3
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#define LMC_ADAP_SSI 4
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#define LMC_ADAP_T1 5
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#define HDLC_HDR_LEN 4
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#define HDLC_ADDR_LEN 1
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#define HDLC_SLARP 0x8035
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#define LMC_MTU 1500
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#define SLARP_LINECHECK 2
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#define LMC_CRC_LEN_16 2 /* 16-bit CRC */
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#define LMC_CRC_LEN_32 4
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#ifdef LMC_HDLC
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/* definition of an hdlc header. */
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struct hdlc_hdr
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{
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u8 address;
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u8 control;
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u16 type;
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};
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/* definition of a slarp header. */
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|
struct slarp
|
|
{
|
|
long code;
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|
union sl
|
|
{
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|
struct
|
|
{
|
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ulong address;
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ulong mask;
|
|
ushort unused;
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} add;
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|
struct
|
|
{
|
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ulong mysequence;
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|
ulong yoursequence;
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ushort reliability;
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ulong time;
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} chk;
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} t;
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};
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#endif /* LMC_HDLC */
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#endif /* _LMC_VAR_H_ */
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