a09e64fbc0
This just leaves include/asm-arm/plat-* to deal with. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
399 lines
10 KiB
C
399 lines
10 KiB
C
/*
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* s3c2443-ac97.c -- ALSA Soc Audio Layer
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*
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* (c) 2007 Wolfson Microelectronics PLC.
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* Graeme Gregory graeme.gregory@wolfsonmicro.com or linux@wolfsonmicro.com
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*
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* Copyright (C) 2005, Sean Choi <sh428.choi@samsung.com>
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/wait.h>
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#include <linux/delay.h>
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#include <linux/clk.h>
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#include <sound/core.h>
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#include <sound/pcm.h>
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#include <sound/ac97_codec.h>
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#include <sound/initval.h>
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#include <sound/soc.h>
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#include <mach/hardware.h>
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#include <asm/plat-s3c/regs-ac97.h>
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#include <mach/regs-gpio.h>
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#include <mach/regs-clock.h>
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#include <mach/audio.h>
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#include <asm/dma.h>
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#include <mach/dma.h>
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#include "s3c24xx-pcm.h"
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#include "s3c24xx-ac97.h"
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struct s3c24xx_ac97_info {
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void __iomem *regs;
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struct clk *ac97_clk;
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};
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static struct s3c24xx_ac97_info s3c24xx_ac97;
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static DECLARE_COMPLETION(ac97_completion);
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static u32 codec_ready;
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static DECLARE_MUTEX(ac97_mutex);
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static unsigned short s3c2443_ac97_read(struct snd_ac97 *ac97,
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unsigned short reg)
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{
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u32 ac_glbctrl;
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u32 ac_codec_cmd;
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u32 stat, addr, data;
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down(&ac97_mutex);
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codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
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ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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ac_codec_cmd = S3C_AC97_CODEC_CMD_READ | AC_CMD_ADDR(reg);
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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udelay(50);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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wait_for_completion(&ac97_completion);
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stat = readl(s3c24xx_ac97.regs + S3C_AC97_STAT);
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addr = (stat >> 16) & 0x7f;
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data = (stat & 0xffff);
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if (addr != reg)
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printk(KERN_ERR "s3c24xx-ac97: req addr = %02x,"
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" rep addr = %02x\n", reg, addr);
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up(&ac97_mutex);
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return (unsigned short)data;
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}
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static void s3c2443_ac97_write(struct snd_ac97 *ac97, unsigned short reg,
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unsigned short val)
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{
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u32 ac_glbctrl;
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u32 ac_codec_cmd;
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down(&ac97_mutex);
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codec_ready = S3C_AC97_GLBSTAT_CODECREADY;
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ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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ac_codec_cmd = AC_CMD_ADDR(reg) | AC_CMD_DATA(val);
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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udelay(50);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl |= S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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wait_for_completion(&ac97_completion);
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ac_codec_cmd = readl(s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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ac_codec_cmd |= S3C_AC97_CODEC_CMD_READ;
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writel(ac_codec_cmd, s3c24xx_ac97.regs + S3C_AC97_CODEC_CMD);
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up(&ac97_mutex);
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}
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static void s3c2443_ac97_warm_reset(struct snd_ac97 *ac97)
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{
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u32 ac_glbctrl;
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = S3C_AC97_GLBCTRL_WARMRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = 0;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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}
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static void s3c2443_ac97_cold_reset(struct snd_ac97 *ac97)
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{
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u32 ac_glbctrl;
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = 0;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA |
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S3C_AC97_GLBCTRL_PCMINTM_DMA | S3C_AC97_GLBCTRL_MICINTM_DMA;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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}
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static irqreturn_t s3c2443_ac97_irq(int irq, void *dev_id)
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{
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int status;
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u32 ac_glbctrl;
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status = readl(s3c24xx_ac97.regs + S3C_AC97_GLBSTAT) & codec_ready;
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if (status) {
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_CODECREADYIE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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complete(&ac97_completion);
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}
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return IRQ_HANDLED;
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}
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struct snd_ac97_bus_ops soc_ac97_ops = {
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.read = s3c2443_ac97_read,
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.write = s3c2443_ac97_write,
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.warm_reset = s3c2443_ac97_warm_reset,
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.reset = s3c2443_ac97_cold_reset,
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};
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static struct s3c2410_dma_client s3c2443_dma_client_out = {
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.name = "AC97 PCM Stereo out"
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};
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static struct s3c2410_dma_client s3c2443_dma_client_in = {
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.name = "AC97 PCM Stereo in"
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};
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static struct s3c2410_dma_client s3c2443_dma_client_micin = {
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.name = "AC97 Mic Mono in"
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};
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static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_out = {
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.client = &s3c2443_dma_client_out,
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.channel = DMACH_PCM_OUT,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
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.dma_size = 4,
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};
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static struct s3c24xx_pcm_dma_params s3c2443_ac97_pcm_stereo_in = {
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.client = &s3c2443_dma_client_in,
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.channel = DMACH_PCM_IN,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
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.dma_size = 4,
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};
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static struct s3c24xx_pcm_dma_params s3c2443_ac97_mic_mono_in = {
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.client = &s3c2443_dma_client_micin,
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.channel = DMACH_MIC_IN,
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.dma_addr = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
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.dma_size = 4,
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};
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static int s3c2443_ac97_probe(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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int ret;
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u32 ac_glbctrl;
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s3c24xx_ac97.regs = ioremap(S3C2440_PA_AC97, 0x100);
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if (s3c24xx_ac97.regs == NULL)
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return -ENXIO;
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s3c24xx_ac97.ac97_clk = clk_get(&pdev->dev, "ac97");
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if (s3c24xx_ac97.ac97_clk == NULL) {
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printk(KERN_ERR "s3c2443-ac97 failed to get ac97_clock\n");
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iounmap(s3c24xx_ac97.regs);
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return -ENODEV;
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}
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clk_enable(s3c24xx_ac97.ac97_clk);
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s3c2410_gpio_cfgpin(S3C2410_GPE0, S3C2443_GPE0_AC_nRESET);
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s3c2410_gpio_cfgpin(S3C2410_GPE1, S3C2443_GPE1_AC_SYNC);
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s3c2410_gpio_cfgpin(S3C2410_GPE2, S3C2443_GPE2_AC_BITCLK);
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s3c2410_gpio_cfgpin(S3C2410_GPE3, S3C2443_GPE3_AC_SDI);
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s3c2410_gpio_cfgpin(S3C2410_GPE4, S3C2443_GPE4_AC_SDO);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = S3C_AC97_GLBCTRL_COLDRESET;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = 0;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ac_glbctrl = S3C_AC97_GLBCTRL_ACLINKON;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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msleep(1);
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ac_glbctrl |= S3C_AC97_GLBCTRL_TRANSFERDATAENABLE;
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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ret = request_irq(IRQ_S3C244x_AC97, s3c2443_ac97_irq,
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IRQF_DISABLED, "AC97", NULL);
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if (ret < 0) {
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printk(KERN_ERR "s3c24xx-ac97: interrupt request failed.\n");
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clk_disable(s3c24xx_ac97.ac97_clk);
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clk_put(s3c24xx_ac97.ac97_clk);
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iounmap(s3c24xx_ac97.regs);
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}
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return ret;
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}
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static void s3c2443_ac97_remove(struct platform_device *pdev,
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struct snd_soc_dai *dai)
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{
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free_irq(IRQ_S3C244x_AC97, NULL);
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clk_disable(s3c24xx_ac97.ac97_clk);
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clk_put(s3c24xx_ac97.ac97_clk);
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iounmap(s3c24xx_ac97.regs);
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}
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static int s3c2443_ac97_hw_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_out;
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else
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cpu_dai->dma_data = &s3c2443_ac97_pcm_stereo_in;
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return 0;
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}
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static int s3c2443_ac97_trigger(struct snd_pcm_substream *substream, int cmd)
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{
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u32 ac_glbctrl;
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
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else
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ac_glbctrl |= S3C_AC97_GLBCTRL_PCMOUTTM_DMA;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
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else
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMOUTTM_MASK;
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break;
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}
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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return 0;
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}
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static int s3c2443_ac97_hw_mic_params(struct snd_pcm_substream *substream,
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struct snd_pcm_hw_params *params)
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{
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struct snd_soc_pcm_runtime *rtd = substream->private_data;
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struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
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if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
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return -ENODEV;
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else
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cpu_dai->dma_data = &s3c2443_ac97_mic_mono_in;
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return 0;
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}
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static int s3c2443_ac97_mic_trigger(struct snd_pcm_substream *substream,
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int cmd)
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{
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u32 ac_glbctrl;
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ac_glbctrl = readl(s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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switch (cmd) {
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case SNDRV_PCM_TRIGGER_START:
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case SNDRV_PCM_TRIGGER_RESUME:
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case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
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ac_glbctrl |= S3C_AC97_GLBCTRL_PCMINTM_DMA;
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break;
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case SNDRV_PCM_TRIGGER_STOP:
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case SNDRV_PCM_TRIGGER_SUSPEND:
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case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
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ac_glbctrl &= ~S3C_AC97_GLBCTRL_PCMINTM_MASK;
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}
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writel(ac_glbctrl, s3c24xx_ac97.regs + S3C_AC97_GLBCTRL);
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return 0;
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}
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#define s3c2443_AC97_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
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SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | \
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SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000)
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struct snd_soc_dai s3c2443_ac97_dai[] = {
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{
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.name = "s3c2443-ac97",
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.id = 0,
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.type = SND_SOC_DAI_AC97,
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.probe = s3c2443_ac97_probe,
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.remove = s3c2443_ac97_remove,
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.playback = {
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.stream_name = "AC97 Playback",
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.channels_min = 2,
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.channels_max = 2,
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.rates = s3c2443_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.capture = {
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.stream_name = "AC97 Capture",
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.channels_min = 2,
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.channels_max = 2,
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.rates = s3c2443_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = {
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.hw_params = s3c2443_ac97_hw_params,
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.trigger = s3c2443_ac97_trigger},
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},
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{
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.name = "pxa2xx-ac97-mic",
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.id = 1,
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.type = SND_SOC_DAI_AC97,
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.capture = {
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.stream_name = "AC97 Mic Capture",
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.channels_min = 1,
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.channels_max = 1,
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.rates = s3c2443_AC97_RATES,
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.formats = SNDRV_PCM_FMTBIT_S16_LE,},
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.ops = {
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.hw_params = s3c2443_ac97_hw_mic_params,
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.trigger = s3c2443_ac97_mic_trigger,},
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},
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};
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EXPORT_SYMBOL_GPL(s3c2443_ac97_dai);
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EXPORT_SYMBOL_GPL(soc_ac97_ops);
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MODULE_AUTHOR("Graeme Gregory");
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MODULE_DESCRIPTION("AC97 driver for the Samsung s3c2443 chip");
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MODULE_LICENSE("GPL");
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