19cfd5c09f
Instead of having board code poke directly into the MPP configuration registers, and separately calling orion5x_gpio_set_valid_pins() to indicate which MPP pins can be used as GPIO pins, introduce a helper function for configuring the roles of each of the MPP pins, and have that helper function handle gpio validity internally. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com> Acked-by: Sylver Bruneau <sylver.bruneau@googlemail.com> Acked-by: Russell King <linux@arm.linux.org.uk>
75 lines
1.4 KiB
C
75 lines
1.4 KiB
C
#ifndef __ARCH_ORION5X_MPP_H
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#define __ARCH_ORION5X_MPP_H
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enum orion5x_mpp_type {
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/*
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* This MPP is unused.
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*/
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MPP_UNUSED,
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/*
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* This MPP pin is used as a generic GPIO pin. Valid for
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* MPPs 0-15 and device bus data pins 16-31. On 5182, also
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* valid for MPPs 16-19.
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*/
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MPP_GPIO,
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/*
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* This MPP is used as PCIe_RST_OUTn pin. Valid for
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* MPP 0 only.
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*/
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MPP_PCIE_RST_OUTn,
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/*
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* This MPP is used as PCI arbiter pin (REQn/GNTn).
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* Valid for MPPs 0-7 only.
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*/
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MPP_PCI_ARB,
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/*
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* This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
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*/
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MPP_PCI_PMEn,
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/*
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* This MPP is used as GigE half-duplex (COL, CRS) or GMII
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* (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
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* MPPs 8-19 only.
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*/
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MPP_GIGE,
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/*
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* This MPP is used as NAND REn/WEn pin. Valid for MPPs
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* 4-7 and 12-17 only, and only on the 5181l/5182/5281.
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*/
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MPP_NAND,
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/*
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* This MPP is used as a PCI clock output pin. Valid for
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* MPPs 6-7 only, and only on the 5181l.
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*/
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MPP_PCI_CLK,
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/*
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* This MPP is used as a SATA presence/activity LED.
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* Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
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*/
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MPP_SATA_LED,
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/*
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* This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
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* Valid for MPPs 16-19 only.
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*/
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MPP_UART,
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};
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struct orion5x_mpp_mode {
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int mpp;
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enum orion5x_mpp_type type;
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};
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void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
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#endif
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