382 lines
10 KiB
C
382 lines
10 KiB
C
/*
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* IOMMU implementation for Broadband Processor Architecture
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* We just establish a linear mapping at boot by setting all the
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* IOPT cache entries in the CPU.
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* The mapping functions should be identical to pci_direct_iommu,
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* except for the handling of the high order bit that is required
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* by the Spider bridge. These should be split into a separate
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* file at the point where we get a different bridge chip.
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*
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* Copyright (C) 2005 IBM Deutschland Entwicklung GmbH,
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* Arnd Bergmann <arndb@de.ibm.com>
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*
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* Based on linear mapping
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* Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#undef DEBUG
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/delay.h>
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#include <linux/string.h>
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#include <linux/init.h>
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#include <linux/bootmem.h>
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#include <linux/mm.h>
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#include <linux/dma-mapping.h>
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#include <asm/sections.h>
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#include <asm/iommu.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include <asm/pci-bridge.h>
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#include <asm/machdep.h>
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#include <asm/pmac_feature.h>
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#include <asm/abs_addr.h>
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#include <asm/system.h>
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#include <asm/ppc-pci.h>
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#include "bpa_iommu.h"
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static inline unsigned long
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get_iopt_entry(unsigned long real_address, unsigned long ioid,
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unsigned long prot)
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{
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return (prot & IOPT_PROT_MASK)
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| (IOPT_COHERENT)
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| (IOPT_ORDER_VC)
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| (real_address & IOPT_RPN_MASK)
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| (ioid & IOPT_IOID_MASK);
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}
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typedef struct {
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unsigned long val;
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} ioste;
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static inline ioste
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mk_ioste(unsigned long val)
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{
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ioste ioste = { .val = val, };
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return ioste;
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}
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static inline ioste
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get_iost_entry(unsigned long iopt_base, unsigned long io_address, unsigned page_size)
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{
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unsigned long ps;
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unsigned long iostep;
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unsigned long nnpt;
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unsigned long shift;
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switch (page_size) {
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case 0x1000000:
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ps = IOST_PS_16M;
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nnpt = 0; /* one page per segment */
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shift = 5; /* segment has 16 iopt entries */
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break;
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case 0x100000:
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ps = IOST_PS_1M;
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nnpt = 0; /* one page per segment */
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shift = 1; /* segment has 256 iopt entries */
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break;
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case 0x10000:
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ps = IOST_PS_64K;
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nnpt = 0x07; /* 8 pages per io page table */
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shift = 0; /* all entries are used */
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break;
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case 0x1000:
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ps = IOST_PS_4K;
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nnpt = 0x7f; /* 128 pages per io page table */
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shift = 0; /* all entries are used */
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break;
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default: /* not a known compile time constant */
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{
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/* BUILD_BUG_ON() is not usable here */
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extern void __get_iost_entry_bad_page_size(void);
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__get_iost_entry_bad_page_size();
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}
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break;
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}
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iostep = iopt_base +
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/* need 8 bytes per iopte */
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(((io_address / page_size * 8)
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/* align io page tables on 4k page boundaries */
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<< shift)
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/* nnpt+1 pages go into each iopt */
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& ~(nnpt << 12));
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nnpt++; /* this seems to work, but the documentation is not clear
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about wether we put nnpt or nnpt-1 into the ioste bits.
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In theory, this can't work for 4k pages. */
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return mk_ioste(IOST_VALID_MASK
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| (iostep & IOST_PT_BASE_MASK)
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| ((nnpt << 5) & IOST_NNPT_MASK)
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| (ps & IOST_PS_MASK));
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}
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/* compute the address of an io pte */
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static inline unsigned long
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get_ioptep(ioste iost_entry, unsigned long io_address)
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{
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unsigned long iopt_base;
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unsigned long page_size;
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unsigned long page_number;
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unsigned long iopt_offset;
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iopt_base = iost_entry.val & IOST_PT_BASE_MASK;
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page_size = iost_entry.val & IOST_PS_MASK;
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/* decode page size to compute page number */
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page_number = (io_address & 0x0fffffff) >> (10 + 2 * page_size);
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/* page number is an offset into the io page table */
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iopt_offset = (page_number << 3) & 0x7fff8ul;
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return iopt_base + iopt_offset;
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}
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/* compute the tag field of the iopt cache entry */
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static inline unsigned long
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get_ioc_tag(ioste iost_entry, unsigned long io_address)
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{
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unsigned long iopte = get_ioptep(iost_entry, io_address);
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return IOPT_VALID_MASK
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| ((iopte & 0x00000000000000ff8ul) >> 3)
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| ((iopte & 0x0000003fffffc0000ul) >> 9);
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}
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/* compute the hashed 6 bit index for the 4-way associative pte cache */
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static inline unsigned long
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get_ioc_hash(ioste iost_entry, unsigned long io_address)
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{
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unsigned long iopte = get_ioptep(iost_entry, io_address);
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return ((iopte & 0x000000000000001f8ul) >> 3)
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^ ((iopte & 0x00000000000020000ul) >> 17)
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^ ((iopte & 0x00000000000010000ul) >> 15)
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^ ((iopte & 0x00000000000008000ul) >> 13)
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^ ((iopte & 0x00000000000004000ul) >> 11)
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^ ((iopte & 0x00000000000002000ul) >> 9)
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^ ((iopte & 0x00000000000001000ul) >> 7);
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}
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/* same as above, but pretend that we have a simpler 1-way associative
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pte cache with an 8 bit index */
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static inline unsigned long
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get_ioc_hash_1way(ioste iost_entry, unsigned long io_address)
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{
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unsigned long iopte = get_ioptep(iost_entry, io_address);
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return ((iopte & 0x000000000000001f8ul) >> 3)
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^ ((iopte & 0x00000000000020000ul) >> 17)
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^ ((iopte & 0x00000000000010000ul) >> 15)
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^ ((iopte & 0x00000000000008000ul) >> 13)
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^ ((iopte & 0x00000000000004000ul) >> 11)
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^ ((iopte & 0x00000000000002000ul) >> 9)
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^ ((iopte & 0x00000000000001000ul) >> 7)
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^ ((iopte & 0x0000000000000c000ul) >> 8);
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}
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static inline ioste
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get_iost_cache(void __iomem *base, unsigned long index)
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{
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unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
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return mk_ioste(in_be64(&p[index]));
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}
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static inline void
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set_iost_cache(void __iomem *base, unsigned long index, ioste ste)
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{
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unsigned long __iomem *p = (base + IOC_ST_CACHE_DIR);
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pr_debug("ioste %02lx was %016lx, store %016lx", index,
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get_iost_cache(base, index).val, ste.val);
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out_be64(&p[index], ste.val);
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pr_debug(" now %016lx\n", get_iost_cache(base, index).val);
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}
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static inline unsigned long
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get_iopt_cache(void __iomem *base, unsigned long index, unsigned long *tag)
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{
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unsigned long __iomem *tags = (void *)(base + IOC_PT_CACHE_DIR);
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unsigned long __iomem *p = (void *)(base + IOC_PT_CACHE_REG);
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*tag = tags[index];
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rmb();
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return *p;
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}
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static inline void
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set_iopt_cache(void __iomem *base, unsigned long index,
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unsigned long tag, unsigned long val)
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{
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unsigned long __iomem *tags = base + IOC_PT_CACHE_DIR;
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unsigned long __iomem *p = base + IOC_PT_CACHE_REG;
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pr_debug("iopt %02lx was v%016lx/t%016lx, store v%016lx/t%016lx\n",
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index, get_iopt_cache(base, index, &oldtag), oldtag, val, tag);
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out_be64(p, val);
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out_be64(&tags[index], tag);
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}
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static inline void
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set_iost_origin(void __iomem *base)
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{
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unsigned long __iomem *p = base + IOC_ST_ORIGIN;
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unsigned long origin = IOSTO_ENABLE | IOSTO_SW;
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pr_debug("iost_origin %016lx, now %016lx\n", in_be64(p), origin);
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out_be64(p, origin);
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}
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static inline void
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set_iocmd_config(void __iomem *base)
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{
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unsigned long __iomem *p = base + 0xc00;
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unsigned long conf;
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conf = in_be64(p);
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pr_debug("iost_conf %016lx, now %016lx\n", conf, conf | IOCMD_CONF_TE);
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out_be64(p, conf | IOCMD_CONF_TE);
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}
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/* FIXME: get these from the device tree */
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#define ioc_base 0x20000511000ull
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#define ioc_mmio_base 0x20000510000ull
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#define ioid 0x48a
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#define iopt_phys_offset (- 0x20000000) /* We have a 512MB offset from the SB */
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#define io_page_size 0x1000000
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static unsigned long map_iopt_entry(unsigned long address)
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{
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switch (address >> 20) {
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case 0x600:
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address = 0x24020000000ull; /* spider i/o */
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break;
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default:
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address += iopt_phys_offset;
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break;
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}
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return get_iopt_entry(address, ioid, IOPT_PROT_RW);
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}
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static void iommu_bus_setup_null(struct pci_bus *b) { }
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static void iommu_dev_setup_null(struct pci_dev *d) { }
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/* initialize the iommu to support a simple linear mapping
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* for each DMA window used by any device. For now, we
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* happen to know that there is only one DMA window in use,
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* starting at iopt_phys_offset. */
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static void bpa_map_iommu(void)
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{
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unsigned long address;
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void __iomem *base;
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ioste ioste;
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unsigned long index;
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base = __ioremap(ioc_base, 0x1000, _PAGE_NO_CACHE);
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pr_debug("%lx mapped to %p\n", ioc_base, base);
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set_iocmd_config(base);
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iounmap(base);
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base = __ioremap(ioc_mmio_base, 0x1000, _PAGE_NO_CACHE);
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pr_debug("%lx mapped to %p\n", ioc_mmio_base, base);
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set_iost_origin(base);
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for (address = 0; address < 0x100000000ul; address += io_page_size) {
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ioste = get_iost_entry(0x10000000000ul, address, io_page_size);
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if ((address & 0xfffffff) == 0) /* segment start */
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set_iost_cache(base, address >> 28, ioste);
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index = get_ioc_hash_1way(ioste, address);
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pr_debug("addr %08lx, index %02lx, ioste %016lx\n",
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address, index, ioste.val);
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set_iopt_cache(base,
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get_ioc_hash_1way(ioste, address),
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get_ioc_tag(ioste, address),
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map_iopt_entry(address));
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}
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iounmap(base);
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}
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static void *bpa_alloc_coherent(struct device *hwdev, size_t size,
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dma_addr_t *dma_handle, gfp_t flag)
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{
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void *ret;
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ret = (void *)__get_free_pages(flag, get_order(size));
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if (ret != NULL) {
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memset(ret, 0, size);
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*dma_handle = virt_to_abs(ret) | BPA_DMA_VALID;
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}
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return ret;
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}
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static void bpa_free_coherent(struct device *hwdev, size_t size,
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void *vaddr, dma_addr_t dma_handle)
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{
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free_pages((unsigned long)vaddr, get_order(size));
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}
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static dma_addr_t bpa_map_single(struct device *hwdev, void *ptr,
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size_t size, enum dma_data_direction direction)
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{
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return virt_to_abs(ptr) | BPA_DMA_VALID;
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}
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static void bpa_unmap_single(struct device *hwdev, dma_addr_t dma_addr,
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size_t size, enum dma_data_direction direction)
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{
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}
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static int bpa_map_sg(struct device *hwdev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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int i;
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for (i = 0; i < nents; i++, sg++) {
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sg->dma_address = (page_to_phys(sg->page) + sg->offset)
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| BPA_DMA_VALID;
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sg->dma_length = sg->length;
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}
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return nents;
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}
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static void bpa_unmap_sg(struct device *hwdev, struct scatterlist *sg,
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int nents, enum dma_data_direction direction)
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{
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}
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static int bpa_dma_supported(struct device *dev, u64 mask)
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{
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return mask < 0x100000000ull;
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}
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void bpa_init_iommu(void)
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{
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bpa_map_iommu();
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/* Direct I/O, IOMMU off */
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ppc_md.iommu_dev_setup = iommu_dev_setup_null;
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ppc_md.iommu_bus_setup = iommu_bus_setup_null;
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pci_dma_ops.alloc_coherent = bpa_alloc_coherent;
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pci_dma_ops.free_coherent = bpa_free_coherent;
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pci_dma_ops.map_single = bpa_map_single;
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pci_dma_ops.unmap_single = bpa_unmap_single;
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pci_dma_ops.map_sg = bpa_map_sg;
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pci_dma_ops.unmap_sg = bpa_unmap_sg;
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pci_dma_ops.dma_supported = bpa_dma_supported;
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}
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