6a4123e581
Minimal support for the 4-bit ECC engine found on DM355, DM365, DA830/OMAP-L137, and similar recent DaVinci-family chips. This is limited to small-page flash for now; there are some page layout issues for large page chips. Note that most boards using this engine (like the DM355 EVM) include 2GiB large page chips. Sanity tested on DM355 EVM after swapping the socketed NAND for a small-page one. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Artem Bityutskiy <Artem.Bityutskiy@nokia.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
85 lines
2.5 KiB
C
85 lines
2.5 KiB
C
/*
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* mach-davinci/nand.h
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*
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* Copyright © 2006 Texas Instruments.
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*
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* Ported to 2.6.23 Copyright © 2008 by
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* Sander Huijsen <Shuijsen@optelecom-nkf.com>
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* Troy Kisky <troy.kisky@boundarydevices.com>
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* Dirk Behme <Dirk.Behme@gmail.com>
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*
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* --------------------------------------------------------------------------
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ARCH_ARM_DAVINCI_NAND_H
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#define __ARCH_ARM_DAVINCI_NAND_H
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#include <linux/mtd/nand.h>
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#define NRCSR_OFFSET 0x00
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#define AWCCR_OFFSET 0x04
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#define A1CR_OFFSET 0x10
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#define NANDFCR_OFFSET 0x60
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#define NANDFSR_OFFSET 0x64
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#define NANDF1ECC_OFFSET 0x70
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/* 4-bit ECC syndrome registers */
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#define NAND_4BIT_ECC_LOAD_OFFSET 0xbc
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#define NAND_4BIT_ECC1_OFFSET 0xc0
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#define NAND_4BIT_ECC2_OFFSET 0xc4
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#define NAND_4BIT_ECC3_OFFSET 0xc8
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#define NAND_4BIT_ECC4_OFFSET 0xcc
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#define NAND_ERR_ADD1_OFFSET 0xd0
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#define NAND_ERR_ADD2_OFFSET 0xd4
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#define NAND_ERR_ERRVAL1_OFFSET 0xd8
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#define NAND_ERR_ERRVAL2_OFFSET 0xdc
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/* NOTE: boards don't need to use these address bits
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* for ALE/CLE unless they support booting from NAND.
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* They're used unless platform data overrides them.
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*/
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#define MASK_ALE 0x08
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#define MASK_CLE 0x10
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struct davinci_nand_pdata { /* platform_data */
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uint32_t mask_ale;
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uint32_t mask_cle;
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/* for packages using two chipselects */
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uint32_t mask_chipsel;
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/* board's default static partition info */
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struct mtd_partition *parts;
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unsigned nr_parts;
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/* none == NAND_ECC_NONE (strongly *not* advised!!)
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* soft == NAND_ECC_SOFT
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* else == NAND_ECC_HW, according to ecc_bits
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*
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* All DaVinci-family chips support 1-bit hardware ECC.
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* Newer ones also support 4-bit ECC, but are awkward
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* using it with large page chips.
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*/
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nand_ecc_modes_t ecc_mode;
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u8 ecc_bits;
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/* e.g. NAND_BUSWIDTH_16 or NAND_USE_FLASH_BBT */
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unsigned options;
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};
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#endif /* __ARCH_ARM_DAVINCI_NAND_H */
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