187 lines
4.6 KiB
C
187 lines
4.6 KiB
C
#ifndef __ASM_MACH_APIC_H
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#define __ASM_MACH_APIC_H
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#include <asm/smp.h>
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#define esr_disable (1)
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#define NO_BALANCE_IRQ (0)
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/* In clustered mode, the high nibble of APIC ID is a cluster number.
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* The low nibble is a 4-bit bitmap. */
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#define XAPIC_DEST_CPUS_SHIFT 4
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#define XAPIC_DEST_CPUS_MASK ((1u << XAPIC_DEST_CPUS_SHIFT) - 1)
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#define XAPIC_DEST_CLUSTER_MASK (XAPIC_DEST_CPUS_MASK << XAPIC_DEST_CPUS_SHIFT)
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#define APIC_DFR_VALUE (APIC_DFR_CLUSTER)
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static inline cpumask_t target_cpus(void)
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{
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/* CPU_MASK_ALL (0xff) has undefined behaviour with
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* dest_LowestPrio mode logical clustered apic interrupt routing
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* Just start on cpu 0. IRQ balancing will spread load
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*/
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return cpumask_of_cpu(0);
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}
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#define TARGET_CPUS (target_cpus())
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#define INT_DELIVERY_MODE (dest_LowestPrio)
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#define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */
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static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
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{
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return 0;
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}
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/* we don't use the phys_cpu_present_map to indicate apicid presence */
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static inline unsigned long check_apicid_present(int bit)
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{
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return 1;
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}
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#define apicid_cluster(apicid) ((apicid) & XAPIC_DEST_CLUSTER_MASK)
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extern u8 bios_cpu_apicid[];
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extern u8 cpu_2_logical_apicid[];
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static inline void init_apic_ldr(void)
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{
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unsigned long val, id;
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int i, count;
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u8 lid;
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u8 my_id = (u8)hard_smp_processor_id();
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u8 my_cluster = (u8)apicid_cluster(my_id);
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/* Create logical APIC IDs by counting CPUs already in cluster. */
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for (count = 0, i = NR_CPUS; --i >= 0; ) {
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lid = cpu_2_logical_apicid[i];
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if (lid != BAD_APICID && apicid_cluster(lid) == my_cluster)
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++count;
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}
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/* We only have a 4 wide bitmap in cluster mode. If a deranged
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* BIOS puts 5 CPUs in one APIC cluster, we're hosed. */
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BUG_ON(count >= XAPIC_DEST_CPUS_SHIFT);
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id = my_cluster | (1UL << count);
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apic_write_around(APIC_DFR, APIC_DFR_VALUE);
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val = apic_read(APIC_LDR) & ~APIC_LDR_MASK;
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val |= SET_APIC_LOGICAL_ID(id);
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apic_write_around(APIC_LDR, val);
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}
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static inline int multi_timer_check(int apic, int irq)
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{
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return 0;
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}
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static inline int apic_id_registered(void)
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{
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return 1;
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}
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static inline void clustered_apic_check(void)
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{
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printk("Enabling APIC mode: Summit. Using %d I/O APICs\n",
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nr_ioapics);
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}
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static inline int apicid_to_node(int logical_apicid)
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{
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return logical_apicid >> 5; /* 2 clusterids per CEC */
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}
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/* Mapping from cpu number to logical apicid */
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static inline int cpu_to_logical_apicid(int cpu)
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{
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if (cpu >= NR_CPUS)
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return BAD_APICID;
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return (int)cpu_2_logical_apicid[cpu];
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}
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static inline int cpu_present_to_apicid(int mps_cpu)
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{
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if (mps_cpu < NR_CPUS)
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return (int)bios_cpu_apicid[mps_cpu];
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else
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return BAD_APICID;
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}
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static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
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{
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/* For clustered we don't have a good way to do this yet - hack */
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return physids_promote(0x0F);
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}
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static inline physid_mask_t apicid_to_cpu_present(int apicid)
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{
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return physid_mask_of_physid(0);
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}
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static inline int mpc_apic_id(struct mpc_config_processor *m,
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struct mpc_config_translation *translation_record)
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{
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printk("Processor #%d %ld:%ld APIC version %d\n",
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m->mpc_apicid,
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(m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8,
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(m->mpc_cpufeature & CPU_MODEL_MASK) >> 4,
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m->mpc_apicver);
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return (m->mpc_apicid);
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}
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static inline void setup_portio_remap(void)
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{
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}
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static inline int check_phys_apicid_present(int boot_cpu_physical_apicid)
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{
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return 1;
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}
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static inline void enable_apic_mode(void)
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{
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}
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static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
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{
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int num_bits_set;
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int cpus_found = 0;
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int cpu;
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int apicid;
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num_bits_set = cpus_weight(cpumask);
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/* Return id to all */
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if (num_bits_set == NR_CPUS)
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return (int) 0xFF;
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/*
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* The cpus in the mask must all be on the apic cluster. If are not
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* on the same apicid cluster return default value of TARGET_CPUS.
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*/
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cpu = first_cpu(cpumask);
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apicid = cpu_to_logical_apicid(cpu);
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while (cpus_found < num_bits_set) {
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if (cpu_isset(cpu, cpumask)) {
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int new_apicid = cpu_to_logical_apicid(cpu);
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if (apicid_cluster(apicid) !=
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apicid_cluster(new_apicid)){
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printk ("%s: Not a valid mask!\n",__FUNCTION__);
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return 0xFF;
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}
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apicid = apicid | new_apicid;
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cpus_found++;
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}
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cpu++;
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}
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return apicid;
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}
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/* cpuid returns the value latched in the HW at reset, not the APIC ID
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* register's value. For any box whose BIOS changes APIC IDs, like
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* clustered APIC systems, we must use hard_smp_processor_id.
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*
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* See Intel's IA-32 SW Dev's Manual Vol2 under CPUID.
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*/
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static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
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{
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return hard_smp_processor_id() >> index_msb;
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}
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#endif /* __ASM_MACH_APIC_H */
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