0009e125b6
Fix otus ISO C90 warnings: drivers/staging/otus/80211core/cmmsta.c:740: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/80211core/coid.c:219: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/80211core/coid.c:1437: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:33: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:53: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:82: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:163: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:219: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:831: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hprw.c:896: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:332: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:1329: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:1565: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:1606: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:1923: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:1997: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2264: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2296: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2330: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2350: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2387: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:2425: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4223: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4283: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4314: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4380: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4425: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4531: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpmain.c:4539: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpusb.c:69: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpusb.c:334: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpusb.c:580: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpreg.c:1774: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpreg.c:2478: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:61: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:80: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:145: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:352: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:393: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:472: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:517: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:592: warning: ISO C90 forbids mixed declarations and code drivers/staging/otus/hal/hpani.c:633: warning: ISO C90 forbids mixed declarations and code Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
731 lines
25 KiB
C
731 lines
25 KiB
C
/*
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* Copyright (c) 2007-2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include "../80211core/cprecomp.h"
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#include "hpani.h"
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#include "hpusb.h"
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extern u16_t zfDelayWriteInternalReg(zdev_t* dev, u32_t addr, u32_t val);
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extern u16_t zfFlushDelayWrite(zdev_t* dev);
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/*
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* Anti noise immunity support. We track phy errors and react
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* to excessive errors by adjusting the noise immunity parameters.
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*/
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/******************************************************************************
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*
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* New Ani Algorithm for Station side only
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*
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*****************************************************************************/
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#define ZM_HAL_NOISE_IMMUNE_MAX 4 /* Max noise immunity level */
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#define ZM_HAL_SPUR_IMMUNE_MAX 7 /* Max spur immunity level */
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#define ZM_HAL_FIRST_STEP_MAX 2 /* Max first step level */
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#define ZM_HAL_ANI_OFDM_TRIG_HIGH 500
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#define ZM_HAL_ANI_OFDM_TRIG_LOW 200
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#define ZM_HAL_ANI_CCK_TRIG_HIGH 200
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#define ZM_HAL_ANI_CCK_TRIG_LOW 100
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#define ZM_HAL_ANI_NOISE_IMMUNE_LVL 4
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#define ZM_HAL_ANI_USE_OFDM_WEAK_SIG TRUE
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#define ZM_HAL_ANI_CCK_WEAK_SIG_THR FALSE
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#define ZM_HAL_ANI_SPUR_IMMUNE_LVL 7
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#define ZM_HAL_ANI_FIRSTEP_LVL 0
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#define ZM_HAL_ANI_RSSI_THR_HIGH 40
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#define ZM_HAL_ANI_RSSI_THR_LOW 7
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#define ZM_HAL_ANI_PERIOD 100
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#define ZM_HAL_EP_RND(x, mul) \
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((((x)%(mul)) >= ((mul)/2)) ? ((x) + ((mul) - 1)) / (mul) : (x)/(mul))
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s32_t BEACON_RSSI(zdev_t* dev)
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{
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s32_t rssi;
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struct zsHpPriv *HpPriv;
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zmw_get_wlan_dev(dev);
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HpPriv = (struct zsHpPriv*)wd->hpPrivate;
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rssi = ZM_HAL_EP_RND(HpPriv->stats.ast_nodestats.ns_avgbrssi, ZM_HAL_RSSI_EP_MULTIPLIER);
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return rssi;
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}
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/*
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* Setup ANI handling. Sets all thresholds and levels to default level AND
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* resets the channel statistics
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*/
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void zfHpAniAttach(zdev_t* dev)
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{
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#define N(a) (sizeof(a) / sizeof(a[0]))
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u32_t i;
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struct zsHpPriv *HpPriv;
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const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
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const int coarseHigh[] = { -14, -14, -14, -14, -12 };
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const int coarseLow[] = { -64, -64, -64, -64, -70 };
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const int firpwr[] = { -78, -78, -78, -78, -80 };
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zmw_get_wlan_dev(dev);
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HpPriv = (struct zsHpPriv*)wd->hpPrivate;
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for (i = 0; i < 5; i++)
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{
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HpPriv->totalSizeDesired[i] = totalSizeDesired[i];
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HpPriv->coarseHigh[i] = coarseHigh[i];
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HpPriv->coarseLow[i] = coarseLow[i];
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HpPriv->firpwr[i] = firpwr[i];
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}
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/* owl has phy counters */
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HpPriv->hasHwPhyCounters = 1;
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memset((char *)&HpPriv->ani, 0, sizeof(HpPriv->ani));
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for (i = 0; i < N(wd->regulationTable.allowChannel); i++)
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{
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/* New ANI stuff */
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HpPriv->ani[i].ofdmTrigHigh = ZM_HAL_ANI_OFDM_TRIG_HIGH;
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HpPriv->ani[i].ofdmTrigLow = ZM_HAL_ANI_OFDM_TRIG_LOW;
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HpPriv->ani[i].cckTrigHigh = ZM_HAL_ANI_CCK_TRIG_HIGH;
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HpPriv->ani[i].cckTrigLow = ZM_HAL_ANI_CCK_TRIG_LOW;
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HpPriv->ani[i].rssiThrHigh = ZM_HAL_ANI_RSSI_THR_HIGH;
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HpPriv->ani[i].rssiThrLow = ZM_HAL_ANI_RSSI_THR_LOW;
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HpPriv->ani[i].ofdmWeakSigDetectOff = !ZM_HAL_ANI_USE_OFDM_WEAK_SIG;
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HpPriv->ani[i].cckWeakSigThreshold = ZM_HAL_ANI_CCK_WEAK_SIG_THR;
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HpPriv->ani[i].spurImmunityLevel = ZM_HAL_ANI_SPUR_IMMUNE_LVL;
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HpPriv->ani[i].firstepLevel = ZM_HAL_ANI_FIRSTEP_LVL;
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if (HpPriv->hasHwPhyCounters)
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{
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HpPriv->ani[i].ofdmPhyErrBase = 0;//AR_PHY_COUNTMAX - ZM_HAL_ANI_OFDM_TRIG_HIGH;
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HpPriv->ani[i].cckPhyErrBase = 0;//AR_PHY_COUNTMAX - ZM_HAL_ANI_CCK_TRIG_HIGH;
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}
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}
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if (HpPriv->hasHwPhyCounters)
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{
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//zm_debug_msg2("Setting OfdmErrBase = 0x", HpPriv->ani[0].ofdmPhyErrBase);
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//zm_debug_msg2("Setting cckErrBase = 0x", HpPriv->ani[0].cckPhyErrBase);
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//OS_REG_WRITE(ah, AR_PHY_ERR_1, HpPriv->ani[0].ofdmPhyErrBase);
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//OS_REG_WRITE(ah, AR_PHY_ERR_2, HpPriv->ani[0].cckPhyErrBase);
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}
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HpPriv->aniPeriod = ZM_HAL_ANI_PERIOD;
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//if (ath_hal_enableANI)
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HpPriv->procPhyErr |= ZM_HAL_PROCESS_ANI;
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HpPriv->stats.ast_nodestats.ns_avgbrssi = ZM_RSSI_DUMMY_MARKER;
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HpPriv->stats.ast_nodestats.ns_avgrssi = ZM_RSSI_DUMMY_MARKER;
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HpPriv->stats.ast_nodestats.ns_avgtxrssi = ZM_RSSI_DUMMY_MARKER;
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#undef N
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}
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/*
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* Control Adaptive Noise Immunity Parameters
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*/
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u8_t zfHpAniControl(zdev_t* dev, ZM_HAL_ANI_CMD cmd, int param)
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{
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#define N(a) (sizeof(a)/sizeof(a[0]))
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typedef s32_t TABLE[];
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struct zsHpPriv *HpPriv;
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struct zsAniState *aniState;
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zmw_get_wlan_dev(dev);
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HpPriv = (struct zsHpPriv*)wd->hpPrivate;
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aniState = HpPriv->curani;
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switch (cmd)
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{
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case ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL:
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{
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u32_t level = param;
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if (level >= N(HpPriv->totalSizeDesired))
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{
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zm_debug_msg1("level out of range, desired level : ", level);
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zm_debug_msg1("max level : ", N(HpPriv->totalSizeDesired));
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return FALSE;
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}
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zfDelayWriteInternalReg(dev, AR_PHY_DESIRED_SZ,
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(HpPriv->regPHYDesiredSZ & ~AR_PHY_DESIRED_SZ_TOT_DES)
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| ((HpPriv->totalSizeDesired[level] << AR_PHY_DESIRED_SZ_TOT_DES_S)
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& AR_PHY_DESIRED_SZ_TOT_DES));
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zfDelayWriteInternalReg(dev, AR_PHY_AGC_CTL1,
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(HpPriv->regPHYAgcCtl1 & ~AR_PHY_AGC_CTL1_COARSE_LOW)
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| ((HpPriv->coarseLow[level] << AR_PHY_AGC_CTL1_COARSE_LOW_S)
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& AR_PHY_AGC_CTL1_COARSE_LOW));
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zfDelayWriteInternalReg(dev, AR_PHY_AGC_CTL1,
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(HpPriv->regPHYAgcCtl1 & ~AR_PHY_AGC_CTL1_COARSE_HIGH)
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| ((HpPriv->coarseHigh[level] << AR_PHY_AGC_CTL1_COARSE_HIGH_S)
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& AR_PHY_AGC_CTL1_COARSE_HIGH));
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zfDelayWriteInternalReg(dev, AR_PHY_FIND_SIG,
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(HpPriv->regPHYFindSig & ~AR_PHY_FIND_SIG_FIRPWR)
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| ((HpPriv->firpwr[level] << AR_PHY_FIND_SIG_FIRPWR_S)
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& AR_PHY_FIND_SIG_FIRPWR));
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zfFlushDelayWrite(dev);
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if (level > aniState->noiseImmunityLevel)
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HpPriv->stats.ast_ani_niup++;
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else if (level < aniState->noiseImmunityLevel)
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HpPriv->stats.ast_ani_nidown++;
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aniState->noiseImmunityLevel = (u8_t)level;
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break;
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}
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case ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:
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{
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const TABLE m1ThreshLow = { 127, 50 };
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const TABLE m2ThreshLow = { 127, 40 };
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const TABLE m1Thresh = { 127, 0x4d };
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const TABLE m2Thresh = { 127, 0x40 };
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const TABLE m2CountThr = { 31, 16 };
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const TABLE m2CountThrLow = { 63, 48 };
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u32_t on = param ? 1 : 0;
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW,
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(HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M1_THRESH_LOW)
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| ((m1ThreshLow[on] << AR_PHY_SFCORR_LOW_M1_THRESH_LOW_S)
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& AR_PHY_SFCORR_LOW_M1_THRESH_LOW));
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW,
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(HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M2_THRESH_LOW)
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| ((m2ThreshLow[on] << AR_PHY_SFCORR_LOW_M2_THRESH_LOW_S)
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& AR_PHY_SFCORR_LOW_M2_THRESH_LOW));
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR,
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(HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M1_THRESH)
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| ((m1Thresh[on] << AR_PHY_SFCORR_M1_THRESH_S)
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& AR_PHY_SFCORR_M1_THRESH));
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR,
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(HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M2_THRESH)
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| ((m2Thresh[on] << AR_PHY_SFCORR_M2_THRESH_S)
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& AR_PHY_SFCORR_M2_THRESH));
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR,
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(HpPriv->regPHYSfcorr & ~AR_PHY_SFCORR_M2COUNT_THR)
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| ((m2CountThr[on] << AR_PHY_SFCORR_M2COUNT_THR_S)
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& AR_PHY_SFCORR_M2COUNT_THR));
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW,
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(HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW)
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| ((m2CountThrLow[on] << AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW_S)
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& AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW));
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if (on)
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{
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW,
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HpPriv->regPHYSfcorrLow | AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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}
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else
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{
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zfDelayWriteInternalReg(dev, AR_PHY_SFCORR_LOW,
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HpPriv->regPHYSfcorrLow & ~AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
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}
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zfFlushDelayWrite(dev);
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if (!on != aniState->ofdmWeakSigDetectOff)
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{
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if (on)
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HpPriv->stats.ast_ani_ofdmon++;
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else
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HpPriv->stats.ast_ani_ofdmoff++;
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aniState->ofdmWeakSigDetectOff = !on;
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}
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break;
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}
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case ZM_HAL_ANI_CCK_WEAK_SIGNAL_THR:
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{
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const TABLE weakSigThrCck = { 8, 6 };
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u32_t high = param ? 1 : 0;
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zfDelayWriteInternalReg(dev, AR_PHY_CCK_DETECT,
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(HpPriv->regPHYCckDetect & ~AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK)
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| ((weakSigThrCck[high] << AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK_S)
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& AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK));
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zfFlushDelayWrite(dev);
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if (high != aniState->cckWeakSigThreshold)
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{
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if (high)
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HpPriv->stats.ast_ani_cckhigh++;
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else
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HpPriv->stats.ast_ani_ccklow++;
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aniState->cckWeakSigThreshold = (u8_t)high;
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}
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break;
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}
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case ZM_HAL_ANI_FIRSTEP_LEVEL:
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{
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const TABLE firstep = { 0, 4, 8 };
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u32_t level = param;
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if (level >= N(firstep))
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{
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zm_debug_msg1("level out of range, desired level : ", level);
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zm_debug_msg1("max level : ", N(firstep));
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return FALSE;
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}
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zfDelayWriteInternalReg(dev, AR_PHY_FIND_SIG,
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(HpPriv->regPHYFindSig & ~AR_PHY_FIND_SIG_FIRSTEP)
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| ((firstep[level] << AR_PHY_FIND_SIG_FIRSTEP_S)
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& AR_PHY_FIND_SIG_FIRSTEP));
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zfFlushDelayWrite(dev);
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if (level > aniState->firstepLevel)
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HpPriv->stats.ast_ani_stepup++;
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else if (level < aniState->firstepLevel)
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HpPriv->stats.ast_ani_stepdown++;
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aniState->firstepLevel = (u8_t)level;
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break;
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}
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case ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL:
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{
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const TABLE cycpwrThr1 = { 2, 4, 6, 8, 10, 12, 14, 16 };
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u32_t level = param;
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if (level >= N(cycpwrThr1))
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{
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zm_debug_msg1("level out of range, desired level : ", level);
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zm_debug_msg1("max level : ", N(cycpwrThr1));
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return FALSE;
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}
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zfDelayWriteInternalReg(dev, AR_PHY_TIMING5,
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(HpPriv->regPHYTiming5 & ~AR_PHY_TIMING5_CYCPWR_THR1)
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| ((cycpwrThr1[level] << AR_PHY_TIMING5_CYCPWR_THR1_S)
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& AR_PHY_TIMING5_CYCPWR_THR1));
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zfFlushDelayWrite(dev);
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if (level > aniState->spurImmunityLevel)
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HpPriv->stats.ast_ani_spurup++;
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else if (level < aniState->spurImmunityLevel)
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HpPriv->stats.ast_ani_spurdown++;
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aniState->spurImmunityLevel = (u8_t)level;
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break;
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}
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case ZM_HAL_ANI_PRESENT:
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break;
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#ifdef AH_PRIVATE_DIAG
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case ZM_HAL_ANI_MODE:
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if (param == 0)
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{
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HpPriv->procPhyErr &= ~ZM_HAL_PROCESS_ANI;
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/* Turn off HW counters if we have them */
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zfHpAniDetach(dev);
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//zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) &~ HAL_RX_FILTER_PHYERR);
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}
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else
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{ /* normal/auto mode */
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HpPriv->procPhyErr |= ZM_HAL_PROCESS_ANI;
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if (HpPriv->hasHwPhyCounters)
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{
|
|
//zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) &~ HAL_RX_FILTER_PHYERR);
|
|
}
|
|
else
|
|
{
|
|
//zfHpSetRxFilter(dev, zfHpGetRxFilter(dev) | HAL_RX_FILTER_PHYERR);
|
|
}
|
|
}
|
|
break;
|
|
case ZM_HAL_ANI_PHYERR_RESET:
|
|
HpPriv->stats.ast_ani_ofdmerrs = 0;
|
|
HpPriv->stats.ast_ani_cckerrs = 0;
|
|
break;
|
|
#endif /* AH_PRIVATE_DIAG */
|
|
default:
|
|
zm_debug_msg1("invalid cmd ", cmd);
|
|
return FALSE;
|
|
}
|
|
return TRUE;
|
|
#undef N
|
|
}
|
|
|
|
void zfHpAniRestart(zdev_t* dev)
|
|
{
|
|
struct zsAniState *aniState;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
aniState = HpPriv->curani;
|
|
|
|
aniState->listenTime = 0;
|
|
if (HpPriv->hasHwPhyCounters)
|
|
{
|
|
//if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX)
|
|
//{
|
|
// aniState->ofdmPhyErrBase = 0;
|
|
// zm_debug_msg0("OFDM Trigger is too high for hw counters");
|
|
//}
|
|
//else
|
|
// aniState->ofdmPhyErrBase = AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
|
|
//if (aniState->cckTrigHigh > AR_PHY_COUNTMAX)
|
|
//{
|
|
// aniState->cckPhyErrBase = 0;
|
|
// zm_debug_msg0("CCK Trigger is too high for hw counters");
|
|
//}
|
|
//else
|
|
// aniState->cckPhyErrBase = AR_PHY_COUNTMAX - aniState->cckTrigHigh;
|
|
//zm_debug_msg2("Writing ofdmbase = 0x", aniState->ofdmPhyErrBase);
|
|
//zm_debug_msg2("Writing cckbase = 0x", aniState->cckPhyErrBase);
|
|
//OS_REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
|
|
//OS_REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
|
|
//OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
|
//OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
|
aniState->ofdmPhyErrBase = 0;
|
|
aniState->cckPhyErrBase = 0;
|
|
}
|
|
aniState->ofdmPhyErrCount = 0;
|
|
aniState->cckPhyErrCount = 0;
|
|
}
|
|
|
|
void zfHpAniOfdmErrTrigger(zdev_t* dev)
|
|
{
|
|
struct zsAniState *aniState;
|
|
s32_t rssi;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
|
|
//HALASSERT(chan != NULL);
|
|
|
|
if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0)
|
|
return;
|
|
|
|
aniState = HpPriv->curani;
|
|
/* First, raise noise immunity level, up to max */
|
|
if (aniState->noiseImmunityLevel < ZM_HAL_NOISE_IMMUNE_MAX)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel + 1);
|
|
return;
|
|
}
|
|
/* then, raise spur immunity level, up to max */
|
|
if (aniState->spurImmunityLevel < ZM_HAL_SPUR_IMMUNE_MAX)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel + 1);
|
|
return;
|
|
}
|
|
rssi = BEACON_RSSI(dev);
|
|
if (rssi > aniState->rssiThrHigh)
|
|
{
|
|
/*
|
|
* Beacon rssi is high, can turn off ofdm weak sig detect.
|
|
*/
|
|
if (!aniState->ofdmWeakSigDetectOff)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, FALSE);
|
|
zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
|
|
return;
|
|
}
|
|
/*
|
|
* If weak sig detect is already off, as last resort, raise
|
|
* first step level
|
|
*/
|
|
if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1);
|
|
return;
|
|
}
|
|
}
|
|
else if (rssi > aniState->rssiThrLow)
|
|
{
|
|
/*
|
|
* Beacon rssi in mid range, need ofdm weak signal detect,
|
|
* but we can raise firststepLevel
|
|
*/
|
|
if (aniState->ofdmWeakSigDetectOff)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, TRUE);
|
|
if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1);
|
|
return;
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* Beacon rssi is low, if in 11b/g mode, turn off ofdm
|
|
* weak sign detction and zero firstepLevel to maximize
|
|
* CCK sensitivity
|
|
*/
|
|
if (wd->frequency < 3000)
|
|
{
|
|
if (!aniState->ofdmWeakSigDetectOff)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, FALSE);
|
|
if (aniState->firstepLevel > 0)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, 0);
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
void zfHpAniCckErrTrigger(zdev_t* dev)
|
|
{
|
|
struct zsAniState *aniState;
|
|
s32_t rssi;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
|
|
//HALASSERT(chan != NULL);
|
|
|
|
if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0)
|
|
return;
|
|
|
|
/* first, raise noise immunity level, up to max */
|
|
aniState = HpPriv->curani;
|
|
if (aniState->noiseImmunityLevel < ZM_HAL_NOISE_IMMUNE_MAX)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL,
|
|
aniState->noiseImmunityLevel + 1);
|
|
return;
|
|
}
|
|
rssi = BEACON_RSSI(dev);
|
|
if (rssi > aniState->rssiThrLow)
|
|
{
|
|
/*
|
|
* Beacon signal in mid and high range, raise firsteplevel.
|
|
*/
|
|
if (aniState->firstepLevel < ZM_HAL_FIRST_STEP_MAX)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel + 1);
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* Beacon rssi is low, zero firstepLevel to maximize
|
|
* CCK sensitivity.
|
|
*/
|
|
if (wd->frequency < 3000)
|
|
{
|
|
if (aniState->firstepLevel > 0)
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, 0);
|
|
}
|
|
}
|
|
}
|
|
|
|
void zfHpAniLowerImmunity(zdev_t* dev)
|
|
{
|
|
struct zsAniState *aniState;
|
|
s32_t rssi;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
aniState = HpPriv->curani;
|
|
|
|
rssi = BEACON_RSSI(dev);
|
|
if (rssi > aniState->rssiThrHigh)
|
|
{
|
|
/*
|
|
* Beacon signal is high, leave ofdm weak signal detection off
|
|
* or it may oscillate. Let it fall through.
|
|
*/
|
|
}
|
|
else if (rssi > aniState->rssiThrLow)
|
|
{
|
|
/*
|
|
* Beacon rssi in mid range, turn on ofdm weak signal
|
|
* detection or lower first step level.
|
|
*/
|
|
if (aniState->ofdmWeakSigDetectOff)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION, TRUE);
|
|
return;
|
|
}
|
|
if (aniState->firstepLevel > 0)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1);
|
|
return;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
* Beacon rssi is low, reduce first step level.
|
|
*/
|
|
if (aniState->firstepLevel > 0)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_FIRSTEP_LEVEL, aniState->firstepLevel - 1);
|
|
return;
|
|
}
|
|
}
|
|
/* then lower spur immunity level, down to zero */
|
|
if (aniState->spurImmunityLevel > 0)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_SPUR_IMMUNITY_LEVEL, aniState->spurImmunityLevel - 1);
|
|
return;
|
|
}
|
|
/*
|
|
* if all else fails, lower noise immunity level down to a min value
|
|
* zero for now
|
|
*/
|
|
if (aniState->noiseImmunityLevel > 0)
|
|
{
|
|
zfHpAniControl(dev, ZM_HAL_ANI_NOISE_IMMUNITY_LEVEL, aniState->noiseImmunityLevel - 1);
|
|
return;
|
|
}
|
|
}
|
|
|
|
#define CLOCK_RATE 44000 /* XXX use mac_usec or similar */
|
|
/* convert HW counter values to ms using 11g clock rate, goo9d enough
|
|
for 11a and Turbo */
|
|
|
|
/*
|
|
* Return an approximation of the time spent ``listening'' by
|
|
* deducting the cycles spent tx'ing and rx'ing from the total
|
|
* cycle count since our last call. A return value <0 indicates
|
|
* an invalid/inconsistent time.
|
|
*/
|
|
s32_t zfHpAniGetListenTime(zdev_t* dev)
|
|
{
|
|
struct zsAniState *aniState;
|
|
u32_t txFrameCount, rxFrameCount, cycleCount;
|
|
s32_t listenTime;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
|
|
txFrameCount = 0;//OS_REG_READ(ah, AR_TFCNT);
|
|
rxFrameCount = 0;//OS_REG_READ(ah, AR_RFCNT);
|
|
cycleCount = 0;//OS_REG_READ(ah, AR_CCCNT);
|
|
|
|
aniState = HpPriv->curani;
|
|
if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount)
|
|
{
|
|
/*
|
|
* Cycle counter wrap (or initial call); it's not possible
|
|
* to accurately calculate a value because the registers
|
|
* right shift rather than wrap--so punt and return 0.
|
|
*/
|
|
listenTime = 0;
|
|
HpPriv->stats.ast_ani_lzero++;
|
|
}
|
|
else
|
|
{
|
|
s32_t ccdelta = cycleCount - aniState->cycleCount;
|
|
s32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
|
|
s32_t tfdelta = txFrameCount - aniState->txFrameCount;
|
|
listenTime = (ccdelta - rfdelta - tfdelta) / CLOCK_RATE;
|
|
}
|
|
aniState->cycleCount = cycleCount;
|
|
aniState->txFrameCount = txFrameCount;
|
|
aniState->rxFrameCount = rxFrameCount;
|
|
return listenTime;
|
|
}
|
|
|
|
/*
|
|
* Do periodic processing. This routine is called from the
|
|
* driver's rx interrupt handler after processing frames.
|
|
*/
|
|
void zfHpAniArPoll(zdev_t* dev, u32_t listenTime, u32_t phyCnt1, u32_t phyCnt2)
|
|
{
|
|
struct zsAniState *aniState;
|
|
//s32_t listenTime;
|
|
struct zsHpPriv *HpPriv;
|
|
|
|
zmw_get_wlan_dev(dev);
|
|
HpPriv = (struct zsHpPriv*)wd->hpPrivate;
|
|
|
|
/*
|
|
* Since we're called from end of rx tasklet, we also check for
|
|
* AR processing now
|
|
*/
|
|
|
|
aniState = HpPriv->curani;
|
|
//HpPriv->stats.ast_nodestats = *stats; /* XXX optimize? */
|
|
|
|
//listenTime = zfHpAniGetListenTime(dev);
|
|
//if (listenTime < 0)
|
|
//{
|
|
// HpPriv->stats.ast_ani_lneg++;
|
|
// /* restart ANI period if listenTime is invalid */
|
|
// zfHpAniRestart(dev);
|
|
// return;
|
|
//}
|
|
/* XXX beware of overflow? */
|
|
aniState->listenTime += listenTime;
|
|
|
|
if (HpPriv->hasHwPhyCounters)
|
|
{
|
|
//u32_t phyCnt1, phyCnt2;
|
|
u32_t ofdmPhyErrCnt, cckPhyErrCnt;
|
|
|
|
/* NB: these are not reset-on-read */
|
|
//phyCnt1 = 0;//OS_REG_READ(ah, AR_PHY_ERR_1);
|
|
//phyCnt2 = 0;//OS_REG_READ(ah, AR_PHY_ERR_2);
|
|
/* XXX sometimes zero, why? */
|
|
//if (phyCnt1 < aniState->ofdmPhyErrBase ||
|
|
// phyCnt2 < aniState->cckPhyErrBase)
|
|
//{
|
|
// if (phyCnt1 < aniState->ofdmPhyErrBase)
|
|
// {
|
|
// zm_debug_msg2("phyCnt1 = 0x", phyCnt1);
|
|
// zm_debug_msg2("resetting counter value to 0x", aniState->ofdmPhyErrBase);
|
|
// //OS_REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
|
|
// //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
|
|
// }
|
|
// if (phyCnt2 < aniState->cckPhyErrBase)
|
|
// {
|
|
// zm_debug_msg2("phyCnt2 = 0x", phyCnt2);
|
|
// zm_debug_msg2("resetting counter value to 0x", aniState->cckPhyErrBase);
|
|
// //OS_REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
|
|
// //OS_REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
|
|
// }
|
|
// return; /* XXX */
|
|
//}
|
|
/* NB: only use ast_ani_*errs with AH_PRIVATE_DIAG */
|
|
//ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
|
|
//HpPriv->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
|
|
//aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
|
|
ofdmPhyErrCnt = phyCnt1;
|
|
HpPriv->stats.ast_ani_ofdmerrs += ofdmPhyErrCnt;
|
|
aniState->ofdmPhyErrCount += ofdmPhyErrCnt;
|
|
|
|
//cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
|
|
//HpPriv->stats.ast_ani_cckerrs += cckPhyErrCnt - aniState->cckPhyErrCount;
|
|
//aniState->cckPhyErrCount = cckPhyErrCnt;
|
|
cckPhyErrCnt = phyCnt2;
|
|
HpPriv->stats.ast_ani_cckerrs += cckPhyErrCnt;
|
|
aniState->cckPhyErrCount += cckPhyErrCnt;
|
|
}
|
|
/*
|
|
* If ani is not enabled, return after we've collected
|
|
* statistics
|
|
*/
|
|
if ((HpPriv->procPhyErr & ZM_HAL_PROCESS_ANI) == 0)
|
|
return;
|
|
if (aniState->listenTime > 5 * HpPriv->aniPeriod)
|
|
{
|
|
/*
|
|
* Check to see if need to lower immunity if
|
|
* 5 aniPeriods have passed
|
|
*/
|
|
if (aniState->ofdmPhyErrCount <= aniState->listenTime *
|
|
aniState->ofdmTrigLow/1000 &&
|
|
aniState->cckPhyErrCount <= aniState->listenTime *
|
|
aniState->cckTrigLow/1000)
|
|
zfHpAniLowerImmunity(dev);
|
|
zfHpAniRestart(dev);
|
|
}
|
|
else if (aniState->listenTime > HpPriv->aniPeriod)
|
|
{
|
|
/* check to see if need to raise immunity */
|
|
if (aniState->ofdmPhyErrCount > aniState->listenTime *
|
|
aniState->ofdmTrigHigh / 1000)
|
|
{
|
|
zfHpAniOfdmErrTrigger(dev);
|
|
zfHpAniRestart(dev);
|
|
}
|
|
else if (aniState->cckPhyErrCount > aniState->listenTime *
|
|
aniState->cckTrigHigh / 1000)
|
|
{
|
|
zfHpAniCckErrTrigger(dev);
|
|
zfHpAniRestart(dev);
|
|
}
|
|
}
|
|
}
|