699a714501
Support for the timers in the Atmel AT91x40 family of CPUs. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Acked-by: Andrew Victor <andrew@sanpeople.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
81 lines
2.5 KiB
C
81 lines
2.5 KiB
C
/*
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* arch/arm/mach-at91/at91x40_time.c
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*
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* (C) Copyright 2007, Greg Ungerer <gerg@snapgear.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/time.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/mach/time.h>
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#include <asm/arch/at91_tc.h>
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/*
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* 3 counter/timer units present.
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*/
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#define AT91_TC_CLK0BASE 0
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#define AT91_TC_CLK1BASE 0x40
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#define AT91_TC_CLK2BASE 0x80
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static unsigned long at91x40_gettimeoffset(void)
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{
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return (at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CV) * 1000000 / (AT91X40_MASTER_CLOCK / 128));
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}
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static irqreturn_t at91x40_timer_interrupt(int irq, void *dev_id)
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{
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at91_sys_read(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_SR);
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timer_tick();
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return IRQ_HANDLED;
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}
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static struct irqaction at91x40_timer_irq = {
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.name = "at91_tick",
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.flags = IRQF_DISABLED | IRQF_TIMER,
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.handler = at91x40_timer_interrupt
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};
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void __init at91x40_timer_init(void)
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{
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unsigned int v;
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at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
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v = at91_sys_read(AT91_TC + AT91_TC_BMR);
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v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
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at91_sys_write(AT91_TC + AT91_TC_BMR, v);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, AT91_TC_CLKDIS);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR, (AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC, (AT91X40_MASTER_CLOCK / 128) / HZ - 1);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
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setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
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at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR, (AT91_TC_SWTRG | AT91_TC_CLKEN));
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}
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struct sys_timer at91x40_timer = {
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.init = at91x40_timer_init,
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.offset = at91x40_gettimeoffset,
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};
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