a8c4c20dfa
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits) [ARM] 3541/2: workaround for PXA27x erratum E7 [ARM] nommu: provide a way for correct control register value selection [ARM] 3705/1: add supersection support to ioremap() [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency [ARM] 3703/1: Add help description for ARCH_EP80219 [ARM] 3678/1: MMC: Make OMAP MMC work [ARM] 3677/1: OMAP: Update H2 defconfig [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1 [ARM] Add section support to ioremap [ARM] Fix sa11x0 SDRAM selection [ARM] Set bit 4 on section mappings correctly depending on CPU [ARM] 3666/1: TRIZEPS4 [1/5] core ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE ARM: OMAP: Update dmtimers ARM: OMAP: Make clock variables static ARM: OMAP: Fix GPMC compilation when DEBUG is defined ARM: OMAP: Mux updates for external DMA and GPIO ...
142 lines
3.8 KiB
C
142 lines
3.8 KiB
C
/*
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* linux/arch/arm/mach-at91rm9200/at91rm9200_time.c
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*
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* Copyright (C) 2003 SAN People
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* Copyright (C) 2003 ATMEL
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/time.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/mach/time.h>
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static unsigned long last_crtr;
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/*
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* The ST_CRTR is updated asynchronously to the master clock. It is therefore
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* necessary to read it twice (with the same value) to ensure accuracy.
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*/
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static inline unsigned long read_CRTR(void) {
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unsigned long x1, x2;
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do {
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x1 = at91_sys_read(AT91_ST_CRTR);
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x2 = at91_sys_read(AT91_ST_CRTR);
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} while (x1 != x2);
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return x1;
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}
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/*
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* Returns number of microseconds since last timer interrupt. Note that interrupts
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* will have been disabled by do_gettimeofday()
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* 'LATCH' is hwclock ticks (see CLOCK_TICK_RATE in timex.h) per jiffy.
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* 'tick' is usecs per jiffy (linux/timex.h).
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*/
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static unsigned long at91rm9200_gettimeoffset(void)
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{
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unsigned long elapsed;
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elapsed = (read_CRTR() - last_crtr) & AT91_ST_ALMV;
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return (unsigned long)(elapsed * (tick_nsec / 1000)) / LATCH;
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}
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/*
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* IRQ handler for the timer.
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*/
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static irqreturn_t at91rm9200_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
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{
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if (at91_sys_read(AT91_ST_SR) & AT91_ST_PITS) { /* This is a shared interrupt */
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write_seqlock(&xtime_lock);
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while (((read_CRTR() - last_crtr) & AT91_ST_ALMV) >= LATCH) {
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timer_tick(regs);
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last_crtr = (last_crtr + LATCH) & AT91_ST_ALMV;
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}
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write_sequnlock(&xtime_lock);
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return IRQ_HANDLED;
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}
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else
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return IRQ_NONE; /* not handled */
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}
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static struct irqaction at91rm9200_timer_irq = {
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.name = "at91_tick",
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.flags = SA_SHIRQ | SA_INTERRUPT | SA_TIMER,
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.handler = at91rm9200_timer_interrupt
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};
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void at91rm9200_timer_reset(void)
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{
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last_crtr = 0;
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/* Real time counter incremented every 30.51758 microseconds */
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at91_sys_write(AT91_ST_RTMR, 1);
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/* Set Period Interval timer */
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at91_sys_write(AT91_ST_PIMR, LATCH);
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/* Enable Period Interval Timer interrupt */
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at91_sys_write(AT91_ST_IER, AT91_ST_PITS);
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}
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/*
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* Set up timer interrupt.
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*/
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void __init at91rm9200_timer_init(void)
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{
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/* Disable all timer interrupts */
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at91_sys_write(AT91_ST_IDR, AT91_ST_PITS | AT91_ST_WDOVF | AT91_ST_RTTINC | AT91_ST_ALMS);
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(void) at91_sys_read(AT91_ST_SR); /* Clear any pending interrupts */
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/* Make IRQs happen for the system timer */
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setup_irq(AT91_ID_SYS, &at91rm9200_timer_irq);
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/* Change the kernel's 'tick' value to 10009 usec. (the default is 10000) */
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tick_usec = (LATCH * 1000000) / CLOCK_TICK_RATE;
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/* Initialize and enable the timer interrupt */
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at91rm9200_timer_reset();
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}
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#ifdef CONFIG_PM
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static void at91rm9200_timer_suspend(void)
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{
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/* disable Period Interval Timer interrupt */
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at91_sys_write(AT91_ST_IDR, AT91_ST_PITS);
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}
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#else
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#define at91rm9200_timer_suspend NULL
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#endif
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struct sys_timer at91rm9200_timer = {
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.init = at91rm9200_timer_init,
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.offset = at91rm9200_gettimeoffset,
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.suspend = at91rm9200_timer_suspend,
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.resume = at91rm9200_timer_reset,
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};
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