8d94cc50aa
Stabilize PIO mode transfers against a range of word sizes and FIFO thresholds and fixes word size setup/override issues. 1) 16 and 32 bit DMA/PIO transfers broken due to timing differences. 2) Potential for bad transfer counts due to transfer size assumptions. 3) Setup function broken is multiple ways. 4) Per transfer bit_per_word changes break DMA setup in pump_tranfers. 5) False positive timeout are not errors. 6) Changes in pxa2xx_spi_chip not effective in calls to setup. 7) Timeout scaling wrong for PXA255 NSSP. 8) Driver leaks memory while busy during unloading. Known issues: SPI_CS_HIGH and SPI_LSB_FIRST settings in struct spi_device are not handled. Testing: This patch has been test against the "random length, random bits/word, random data (verified on loopback) and stepped baud rate by octaves (3.6MHz to 115kHz)" test. It is robust in PIO mode, using any combination of tx and rx thresholds, and also in DMA mode (which internally computes the thresholds). Much thanks to Ned Forrester for exhaustive reviews, fixes and testing. The driver is substantially better for his efforts. Signed-off-by: Stephen Street <stephen@streetfiresound.com> Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
69 lines
2.2 KiB
C
69 lines
2.2 KiB
C
/*
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* Copyright (C) 2005 Stephen Street / StreetFire Sound Labs
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef PXA2XX_SPI_H_
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#define PXA2XX_SPI_H_
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#define PXA2XX_CS_ASSERT (0x01)
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#define PXA2XX_CS_DEASSERT (0x02)
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#if defined(CONFIG_PXA25x)
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#define CLOCK_SPEED_HZ 3686400
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#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/2/(x+1))<<8)&0x0000ff00)
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#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
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#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
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#elif defined(CONFIG_PXA27x)
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#define CLOCK_SPEED_HZ 13000000
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#define SSP1_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
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#define SSP2_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
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#define SSP3_SerClkDiv(x) (((CLOCK_SPEED_HZ/(x+1))<<8)&0x000fff00)
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#endif
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#define SSP1_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(1)))))
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#define SSP2_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(2)))))
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#define SSP3_VIRT ((void *)(io_p2v(__PREG(SSCR0_P(3)))))
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enum pxa_ssp_type {
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SSP_UNDEFINED = 0,
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PXA25x_SSP, /* pxa 210, 250, 255, 26x */
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PXA25x_NSSP, /* pxa 255, 26x (including ASSP) */
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PXA27x_SSP,
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};
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/* device.platform_data for SSP controller devices */
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struct pxa2xx_spi_master {
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enum pxa_ssp_type ssp_type;
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u32 clock_enable;
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u16 num_chipselect;
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u8 enable_dma;
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};
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/* spi_board_info.controller_data for SPI slave devices,
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* copied to spi_device.platform_data ... mostly for dma tuning
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*/
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struct pxa2xx_spi_chip {
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u8 tx_threshold;
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u8 rx_threshold;
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u8 dma_burst_size;
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u32 timeout;
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u8 enable_loopback;
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void (*cs_control)(u32 command);
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};
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#endif /*PXA2XX_SPI_H_*/
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