1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/*
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* arch/v850/kernel/fpga85e2c.h -- Machine-dependent defs for
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* FPGA implementation of V850E2/NA85E2C
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*
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* Copyright (C) 2002,03 NEC Electronics Corporation
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* Copyright (C) 2002,03 Miles Bader <miles@gnu.org>
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*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file COPYING in the main directory of this
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* archive for more details.
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*
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* Written by Miles Bader <miles@gnu.org>
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/bitops.h>
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#include <asm/atomic.h>
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#include <asm/page.h>
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#include <asm/machdep.h>
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#include "mach.h"
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extern void memcons_setup (void);
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#define REG_DUMP_ADDR 0x220000
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extern struct irqaction reg_snap_action; /* fwd decl */
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void __init mach_early_init (void)
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{
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int i;
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const u32 *src;
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register u32 *dst asm ("ep");
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extern u32 _intv_end, _intv_load_start;
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/* Set bus sizes: CS0 32-bit, CS1 16-bit, CS7 8-bit,
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everything else 32-bit. */
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V850E2_BSC = 0x2AA6;
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for (i = 2; i <= 6; i++)
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CSDEV(i) = 0; /* 32 bit */
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/* Ensure that the simulator halts on a panic, instead of going
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into an infinite loop inside the panic function. */
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panic_timeout = -1;
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/* Move the interrupt vectors into their real location. Note that
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any relocations there are relative to the real location, so we
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don't have to fix anything up. We use a loop instead of calling
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memcpy to keep this a leaf function (to avoid a function
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prologue being generated). */
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dst = 0x10; /* &_intv_start + 0x10. */
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src = &_intv_load_start;
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do {
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u32 t0 = src[0], t1 = src[1], t2 = src[2], t3 = src[3];
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u32 t4 = src[4], t5 = src[5], t6 = src[6], t7 = src[7];
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dst[0] = t0; dst[1] = t1; dst[2] = t2; dst[3] = t3;
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dst[4] = t4; dst[5] = t5; dst[6] = t6; dst[7] = t7;
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dst += 8;
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src += 8;
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} while (dst < &_intv_end);
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}
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void __init mach_setup (char **cmdline)
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{
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memcons_setup ();
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/* Setup up NMI0 to copy the registers to a known memory location.
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The FGPA board has a button that produces NMI0 when pressed, so
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this allows us to push the button, and then look at memory to see
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what's in the registers (there's no other way to easily do so).
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We have to use `setup_irq' instead of `request_irq' because it's
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still too early to do memory allocation. */
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setup_irq (IRQ_NMI (0), ®_snap_action);
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}
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void mach_get_physical_ram (unsigned long *ram_start, unsigned long *ram_len)
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{
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*ram_start = ERAM_ADDR;
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*ram_len = ERAM_SIZE;
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}
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void __init mach_sched_init (struct irqaction *timer_action)
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{
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/* Setup up the timer interrupt. The FPGA peripheral control
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registers _only_ work with single-bit writes (set1/clr1)! */
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__clear_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);
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__clear_bit (RPU_GTMC_CLK_BIT, &RPU_GTMC);
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__set_bit (RPU_GTMC_CE_BIT, &RPU_GTMC);
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/* We use the first RPU interrupt, which occurs every 8.192ms. */
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setup_irq (IRQ_RPU (0), timer_action);
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}
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void mach_gettimeofday (struct timespec *tv)
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{
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tv->tv_sec = 0;
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tv->tv_nsec = 0;
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}
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void machine_halt (void) __attribute__ ((noreturn));
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void machine_halt (void)
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{
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for (;;) {
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DWC(0) = 0x7777;
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DWC(1) = 0x7777;
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ASC = 0xffff;
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FLGREG(0) = 1; /* Halt immediately. */
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asm ("di; halt; nop; nop; nop; nop; nop");
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}
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}
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EXPORT_SYMBOL(machine_halt);
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void machine_restart (char *__unused)
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{
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machine_halt ();
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}
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EXPORT_SYMBOL(machine_restart);
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void machine_power_off (void)
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{
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machine_halt ();
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}
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EXPORT_SYMBOL(machine_power_off);
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/* Interrupts */
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struct v850e_intc_irq_init irq_inits[] = {
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{ "IRQ", 0, NUM_MACH_IRQS, 1, 7 },
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{ "RPU", IRQ_RPU(0), IRQ_RPU_NUM, 1, 6 },
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{ 0 }
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};
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#define NUM_IRQ_INITS ((sizeof irq_inits / sizeof irq_inits[0]) - 1)
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struct hw_interrupt_type hw_itypes[NUM_IRQ_INITS];
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/* Initialize interrupts. */
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void __init mach_init_irqs (void)
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{
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v850e_intc_init_irq_types (irq_inits, hw_itypes);
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}
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/* An interrupt handler that copies the registers to a known memory location,
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for debugging purposes. */
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static void make_reg_snap (int irq, void *dummy, struct pt_regs *regs)
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{
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(*(unsigned *)REG_DUMP_ADDR)++;
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(*(struct pt_regs *)(REG_DUMP_ADDR + sizeof (unsigned))) = *regs;
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}
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static int reg_snap_dev_id;
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static struct irqaction reg_snap_action = {
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make_reg_snap, 0, CPU_MASK_NONE, "reg_snap", ®_snap_dev_id, 0
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};
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