a24ceab4f4
The primary aim of this patchset is to remove maintenances problems caused by the irq infrastructure. The two big issues I address are an artificially small cap on the number of irqs, and that MSI assumes vector == irq. My primary focus is on x86_64 but I have touched other architectures where necessary to keep them from breaking. - To increase the number of irqs I modify the code to look at the (cpu, vector) pair instead of just looking at the vector. With a large number of irqs available systems with a large irq count no longer need to compress their irq numbers to fit. Removing a lot of brittle special cases. For acpi guys the result is that irq == gsi. - Addressing the fact that MSI assumes irq == vector takes a few more patches. But suffice it to say when I am done none of the generic irq code even knows what a vector is. In quick testing on a large Unisys x86_64 machine we stumbled over at least one driver that assumed that NR_IRQS could always fit into an 8 bit number. This driver is clearly buggy today. But this has become a class of bugs that it is now much easier to hit. This patch: This is a minor space optimization. In practice I don't think this has any affect because of our alignment constraints and the other fields but there is not point in chewing up an uncessary word and since we already read the flag field this should improve the cache hit ratio of the irq handler. Signed-off-by: Eric W. Biederman <ebiederm@xmission.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Rajesh Shah <rajesh.shah@intel.com> Cc: Andi Kleen <ak@muc.de> Cc: "Protasevich, Natalie" <Natalie.Protasevich@UNISYS.com> Cc: "Luck, Tony" <tony.luck@intel.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
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#include <linux/irq.h>
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void set_pending_irq(unsigned int irq, cpumask_t mask)
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{
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struct irq_desc *desc = irq_desc + irq;
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unsigned long flags;
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spin_lock_irqsave(&desc->lock, flags);
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desc->status |= IRQ_MOVE_PENDING;
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irq_desc[irq].pending_mask = mask;
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spin_unlock_irqrestore(&desc->lock, flags);
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}
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void move_native_irq(int irq)
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{
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struct irq_desc *desc = irq_desc + irq;
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cpumask_t tmp;
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if (likely(!(desc->status & IRQ_MOVE_PENDING)))
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return;
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/*
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* Paranoia: cpu-local interrupts shouldn't be calling in here anyway.
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*/
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if (CHECK_IRQ_PER_CPU(desc->status)) {
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WARN_ON(1);
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return;
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}
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desc->status &= ~IRQ_MOVE_PENDING;
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if (unlikely(cpus_empty(irq_desc[irq].pending_mask)))
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return;
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if (!desc->chip->set_affinity)
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return;
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assert_spin_locked(&desc->lock);
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cpus_and(tmp, irq_desc[irq].pending_mask, cpu_online_map);
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/*
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* If there was a valid mask to work with, please
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* do the disable, re-program, enable sequence.
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* This is *not* particularly important for level triggered
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* but in a edge trigger case, we might be setting rte
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* when an active trigger is comming in. This could
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* cause some ioapics to mal-function.
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* Being paranoid i guess!
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*/
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if (likely(!cpus_empty(tmp))) {
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if (likely(!(desc->status & IRQ_DISABLED)))
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desc->chip->disable(irq);
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desc->chip->set_affinity(irq,tmp);
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if (likely(!(desc->status & IRQ_DISABLED)))
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desc->chip->enable(irq);
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}
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cpus_clear(irq_desc[irq].pending_mask);
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}
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