090f848da0
Add support for the UDIVSLOT register on the newer UART blocks which gives the capability of 1/16ths adjustment to the baud rate. Signed-off-by: Ben Dooks <ben-linux@fluff.org>
153 lines
3.7 KiB
C
153 lines
3.7 KiB
C
/* linux/drivers/serial/s3c6400.c
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*
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* Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
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*
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* Copyright 2008 Openmoko, Inc.
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* Copyright 2008 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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* http://armlinux.simtec.co.uk/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/io.h>
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#include <linux/platform_device.h>
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#include <linux/init.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <asm/irq.h>
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#include <mach/hardware.h>
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#include <plat/regs-serial.h>
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#include "samsung.h"
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static int s3c6400_serial_setsource(struct uart_port *port,
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struct s3c24xx_uart_clksrc *clk)
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{
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unsigned long ucon = rd_regl(port, S3C2410_UCON);
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if (strcmp(clk->name, "uclk0") == 0) {
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ucon &= ~S3C6400_UCON_CLKMASK;
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ucon |= S3C6400_UCON_UCLK0;
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} else if (strcmp(clk->name, "uclk1") == 0)
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ucon |= S3C6400_UCON_UCLK1;
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else if (strcmp(clk->name, "pclk") == 0) {
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/* See notes about transitioning from UCLK to PCLK */
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ucon &= ~S3C6400_UCON_UCLK0;
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} else {
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printk(KERN_ERR "unknown clock source %s\n", clk->name);
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return -EINVAL;
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}
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wr_regl(port, S3C2410_UCON, ucon);
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return 0;
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}
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static int s3c6400_serial_getsource(struct uart_port *port,
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struct s3c24xx_uart_clksrc *clk)
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{
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u32 ucon = rd_regl(port, S3C2410_UCON);
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clk->divisor = 1;
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switch (ucon & S3C6400_UCON_CLKMASK) {
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case S3C6400_UCON_UCLK0:
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clk->name = "uclk0";
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break;
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case S3C6400_UCON_UCLK1:
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clk->name = "uclk1";
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break;
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case S3C6400_UCON_PCLK:
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case S3C6400_UCON_PCLK2:
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clk->name = "pclk";
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break;
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}
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return 0;
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}
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static int s3c6400_serial_resetport(struct uart_port *port,
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struct s3c2410_uartcfg *cfg)
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{
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unsigned long ucon = rd_regl(port, S3C2410_UCON);
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dbg("s3c6400_serial_resetport: port=%p (%08lx), cfg=%p\n",
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port, port->mapbase, cfg);
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/* ensure we don't change the clock settings... */
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ucon &= S3C6400_UCON_CLKMASK;
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wr_regl(port, S3C2410_UCON, ucon | cfg->ucon);
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wr_regl(port, S3C2410_ULCON, cfg->ulcon);
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/* reset both fifos */
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wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH);
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wr_regl(port, S3C2410_UFCON, cfg->ufcon);
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return 0;
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}
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static struct s3c24xx_uart_info s3c6400_uart_inf = {
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.name = "Samsung S3C6400 UART",
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.type = PORT_S3C6400,
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.fifosize = 64,
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.has_divslot = 1,
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.rx_fifomask = S3C2440_UFSTAT_RXMASK,
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.rx_fifoshift = S3C2440_UFSTAT_RXSHIFT,
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.rx_fifofull = S3C2440_UFSTAT_RXFULL,
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.tx_fifofull = S3C2440_UFSTAT_TXFULL,
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.tx_fifomask = S3C2440_UFSTAT_TXMASK,
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.tx_fifoshift = S3C2440_UFSTAT_TXSHIFT,
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.get_clksrc = s3c6400_serial_getsource,
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.set_clksrc = s3c6400_serial_setsource,
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.reset_port = s3c6400_serial_resetport,
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};
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/* device management */
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static int s3c6400_serial_probe(struct platform_device *dev)
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{
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dbg("s3c6400_serial_probe: dev=%p\n", dev);
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return s3c24xx_serial_probe(dev, &s3c6400_uart_inf);
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}
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static struct platform_driver s3c6400_serial_drv = {
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.probe = s3c6400_serial_probe,
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.remove = s3c24xx_serial_remove,
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.driver = {
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.name = "s3c6400-uart",
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.owner = THIS_MODULE,
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},
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};
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s3c24xx_console_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
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static int __init s3c6400_serial_init(void)
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{
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return s3c24xx_serial_init(&s3c6400_serial_drv, &s3c6400_uart_inf);
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}
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static void __exit s3c6400_serial_exit(void)
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{
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platform_driver_unregister(&s3c6400_serial_drv);
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}
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module_init(s3c6400_serial_init);
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module_exit(s3c6400_serial_exit);
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MODULE_DESCRIPTION("Samsung S3C6400,S3C6410 SoC Serial port driver");
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MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:s3c6400-uart");
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