13fe24f37d
http://blackfin.uclinux.org/gf/project/uclinux-dist/tracker/?action=TrackerItemEdit&tracker_item_id=3719 When the CPLBs get a miss, we do: - find a victim in the HW table - remove the victim - find the replacement in the software table - put it into the HW table. If we can't find a replacement in the software table, we accidently leave a duplicate in the HW table. This patch ensures that duplicate is marked as not valid. What we should do is find the replacement in the software table, before we find a victim in the HW table - but its too late in the release cycle to do that much restructuring of this code. Rather that duplicate code, connect Hardware Errors (irq5) into trap_c, so user space processes get killed properly. The rest of irq_panic() can be moved into traps.c (later) There is still a small corner case that causes problems when a pheriperal interrupt goes off a single cycle before a user space hardware error. This causes a kernel panic, rather than the user space process being killed. But, this checkin makes things work in 99.9% of the cases, and is a vast improvement from what is there today (which fails 100% of the time). Signed-off-by: Robin Getz <robin.getz@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
132 lines
5.0 KiB
C
132 lines
5.0 KiB
C
/*
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* linux/include/asm/traps.h
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*
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* Copyright (C) 1993 Hamish Macdonald
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*
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* Lineo, Inc Jul 2001 Tony Kou
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file COPYING in the main directory of this archive
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* for more details.
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*/
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#ifndef _BFIN_TRAPS_H
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#define _BFIN_TRAPS_H
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#define VEC_SYS (0)
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#define VEC_EXCPT01 (1)
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#define VEC_EXCPT02 (2)
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#define VEC_EXCPT03 (3)
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#define VEC_EXCPT04 (4)
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#define VEC_EXCPT05 (5)
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#define VEC_EXCPT06 (6)
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#define VEC_EXCPT07 (7)
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#define VEC_EXCPT08 (8)
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#define VEC_EXCPT09 (9)
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#define VEC_EXCPT10 (10)
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#define VEC_EXCPT11 (11)
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#define VEC_EXCPT12 (12)
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#define VEC_EXCPT13 (13)
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#define VEC_EXCPT14 (14)
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#define VEC_EXCPT15 (15)
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#define VEC_STEP (16)
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#define VEC_OVFLOW (17)
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#define VEC_UNDEF_I (33)
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#define VEC_ILGAL_I (34)
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#define VEC_CPLB_VL (35)
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#define VEC_MISALI_D (36)
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#define VEC_UNCOV (37)
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#define VEC_CPLB_M (38)
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#define VEC_CPLB_MHIT (39)
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#define VEC_WATCH (40)
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#define VEC_ISTRU_VL (41) /*ADSP-BF535 only (MH) */
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#define VEC_MISALI_I (42)
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#define VEC_CPLB_I_VL (43)
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#define VEC_CPLB_I_M (44)
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#define VEC_CPLB_I_MHIT (45)
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#define VEC_ILL_RES (46) /* including unvalid supervisor mode insn */
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/* The hardware reserves (63) for future use - we use it to tell our
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* normal exception handling code we have a hardware error
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*/
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#define VEC_HWERR (63)
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#ifndef __ASSEMBLY__
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#define HWC_x2(level) \
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"System MMR Error\n" \
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level " - An error occurred due to an invalid access to an System MMR location\n" \
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level " Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
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level " or a 16-bit register is accessed with a 32-bit instruction.\n"
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#define HWC_x3(level) \
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"External Memory Addressing Error\n"
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#define HWC_x12(level) \
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"Performance Monitor Overflow\n"
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#define HWC_x18(level) \
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"RAISE 5 instruction\n" \
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level " Software issued a RAISE 5 instruction to invoke the Hardware\n"
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#define HWC_default(level) \
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"Reserved\n"
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#define EXC_0x03(level) \
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"Application stack overflow\n" \
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level " - Please increase the stack size of the application using elf2flt -s option,\n" \
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level " and/or reduce the stack use of the application.\n"
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#define EXC_0x10(level) \
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"Single step\n" \
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level " - When the processor is in single step mode, every instruction\n" \
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level " generates an exception. Primarily used for debugging.\n"
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#define EXC_0x11(level) \
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"Exception caused by a trace buffer full condition\n" \
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level " - The processor takes this exception when the trace\n" \
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level " buffer overflows (only when enabled by the Trace Unit Control register).\n"
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#define EXC_0x21(level) \
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"Undefined instruction\n" \
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level " - May be used to emulate instructions that are not defined for\n" \
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level " a particular processor implementation.\n"
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#define EXC_0x22(level) \
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"Illegal instruction combination\n" \
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level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
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level " Processor Instruction Set Reference.\n"
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#define EXC_0x23(level) \
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"Data access CPLB protection violation\n" \
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level " - Attempted read or write to Supervisor resource,\n" \
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level " or illegal data memory access. \n"
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#define EXC_0x24(level) \
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"Data access misaligned address violation\n" \
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level " - Attempted misaligned data memory or data cache access.\n"
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#define EXC_0x25(level) \
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"Unrecoverable event\n" \
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level " - For example, an exception generated while processing a previous exception.\n"
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#define EXC_0x26(level) \
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"Data access CPLB miss\n" \
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level " - Used by the MMU to signal a CPLB miss on a data access.\n"
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#define EXC_0x27(level) \
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"Data access multiple CPLB hits\n" \
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level " - More than one CPLB entry matches data fetch address.\n"
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#define EXC_0x28(level) \
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"Program Sequencer Exception caused by an emulation watchpoint match\n" \
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level " - There is a watchpoint match, and one of the EMUSW\n" \
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level " bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
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#define EXC_0x2A(level) \
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"Instruction fetch misaligned address violation\n" \
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level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
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level " exception, the return address provided in RETX is the destination address which is\n" \
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level " misaligned, rather than the address of the offending instruction.\n"
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#define EXC_0x2B(level) \
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"CPLB protection violation\n" \
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level " - Illegal instruction fetch access (memory protection violation).\n"
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#define EXC_0x2C(level) \
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"Instruction fetch CPLB miss\n" \
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level " - CPLB miss on an instruction fetch.\n"
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#define EXC_0x2D(level) \
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"Instruction fetch multiple CPLB hits\n" \
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level " - More than one CPLB entry matches instruction fetch address.\n"
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#define EXC_0x2E(level) \
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"Illegal use of supervisor resource\n" \
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level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
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level " Supervisor resources are registers and instructions that are reserved\n" \
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level " for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
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level " only instructions.\n"
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#endif /* __ASSEMBLY__ */
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#endif /* _BFIN_TRAPS_H */
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