1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
439 lines
13 KiB
C
439 lines
13 KiB
C
#ifndef __MV643XX_ETH_H__
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#define __MV643XX_ETH_H__
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#include <linux/version.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/mv643xx.h>
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#define BIT0 0x00000001
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#define BIT1 0x00000002
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#define BIT2 0x00000004
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#define BIT3 0x00000008
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#define BIT4 0x00000010
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#define BIT5 0x00000020
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#define BIT6 0x00000040
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#define BIT7 0x00000080
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#define BIT8 0x00000100
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#define BIT9 0x00000200
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#define BIT10 0x00000400
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#define BIT11 0x00000800
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#define BIT12 0x00001000
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#define BIT13 0x00002000
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#define BIT14 0x00004000
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#define BIT15 0x00008000
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#define BIT16 0x00010000
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#define BIT17 0x00020000
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#define BIT18 0x00040000
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#define BIT19 0x00080000
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#define BIT20 0x00100000
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#define BIT21 0x00200000
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#define BIT22 0x00400000
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#define BIT23 0x00800000
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#define BIT24 0x01000000
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#define BIT25 0x02000000
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#define BIT26 0x04000000
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#define BIT27 0x08000000
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#define BIT28 0x10000000
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#define BIT29 0x20000000
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#define BIT30 0x40000000
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#define BIT31 0x80000000
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/*
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* The first part is the high level driver of the gigE ethernet ports.
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*/
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/* Checksum offload for Tx works for most packets, but
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* fails if previous packet sent did not use hw csum
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*/
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#undef MV643XX_CHECKSUM_OFFLOAD_TX
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#define MV643XX_NAPI
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#define MV643XX_TX_FAST_REFILL
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#undef MV643XX_RX_QUEUE_FILL_ON_TASK /* Does not work, yet */
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#undef MV643XX_COAL
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/*
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* Number of RX / TX descriptors on RX / TX rings.
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* Note that allocating RX descriptors is done by allocating the RX
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* ring AND a preallocated RX buffers (skb's) for each descriptor.
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* The TX descriptors only allocates the TX descriptors ring,
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* with no pre allocated TX buffers (skb's are allocated by higher layers.
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*/
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/* Default TX ring size is 1000 descriptors */
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#define MV643XX_DEFAULT_TX_QUEUE_SIZE 1000
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/* Default RX ring size is 400 descriptors */
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#define MV643XX_DEFAULT_RX_QUEUE_SIZE 400
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#define MV643XX_TX_COAL 100
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#ifdef MV643XX_COAL
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#define MV643XX_RX_COAL 100
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#endif
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/*
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* The second part is the low level driver of the gigE ethernet ports.
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*/
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/*
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* Header File for : MV-643xx network interface header
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*
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* DESCRIPTION:
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* This header file contains macros typedefs and function declaration for
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* the Marvell Gig Bit Ethernet Controller.
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*
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* DEPENDENCIES:
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* None.
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*
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*/
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/* MAC accepet/reject macros */
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#define ACCEPT_MAC_ADDR 0
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#define REJECT_MAC_ADDR 1
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/* Buffer offset from buffer pointer */
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#define RX_BUF_OFFSET 0x2
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/* Gigabit Ethernet Unit Global Registers */
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/* MIB Counters register definitions */
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_LOW 0x0
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#define ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH 0x4
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#define ETH_MIB_BAD_OCTETS_RECEIVED 0x8
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#define ETH_MIB_INTERNAL_MAC_TRANSMIT_ERR 0xc
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#define ETH_MIB_GOOD_FRAMES_RECEIVED 0x10
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#define ETH_MIB_BAD_FRAMES_RECEIVED 0x14
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#define ETH_MIB_BROADCAST_FRAMES_RECEIVED 0x18
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#define ETH_MIB_MULTICAST_FRAMES_RECEIVED 0x1c
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#define ETH_MIB_FRAMES_64_OCTETS 0x20
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#define ETH_MIB_FRAMES_65_TO_127_OCTETS 0x24
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#define ETH_MIB_FRAMES_128_TO_255_OCTETS 0x28
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#define ETH_MIB_FRAMES_256_TO_511_OCTETS 0x2c
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#define ETH_MIB_FRAMES_512_TO_1023_OCTETS 0x30
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#define ETH_MIB_FRAMES_1024_TO_MAX_OCTETS 0x34
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#define ETH_MIB_GOOD_OCTETS_SENT_LOW 0x38
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#define ETH_MIB_GOOD_OCTETS_SENT_HIGH 0x3c
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#define ETH_MIB_GOOD_FRAMES_SENT 0x40
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#define ETH_MIB_EXCESSIVE_COLLISION 0x44
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#define ETH_MIB_MULTICAST_FRAMES_SENT 0x48
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#define ETH_MIB_BROADCAST_FRAMES_SENT 0x4c
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#define ETH_MIB_UNREC_MAC_CONTROL_RECEIVED 0x50
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#define ETH_MIB_FC_SENT 0x54
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#define ETH_MIB_GOOD_FC_RECEIVED 0x58
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#define ETH_MIB_BAD_FC_RECEIVED 0x5c
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#define ETH_MIB_UNDERSIZE_RECEIVED 0x60
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#define ETH_MIB_FRAGMENTS_RECEIVED 0x64
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#define ETH_MIB_OVERSIZE_RECEIVED 0x68
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#define ETH_MIB_JABBER_RECEIVED 0x6c
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#define ETH_MIB_MAC_RECEIVE_ERROR 0x70
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#define ETH_MIB_BAD_CRC_EVENT 0x74
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#define ETH_MIB_COLLISION 0x78
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#define ETH_MIB_LATE_COLLISION 0x7c
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/* Port serial status reg (PSR) */
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#define ETH_INTERFACE_GMII_MII 0
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#define ETH_INTERFACE_PCM BIT0
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#define ETH_LINK_IS_DOWN 0
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#define ETH_LINK_IS_UP BIT1
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#define ETH_PORT_AT_HALF_DUPLEX 0
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#define ETH_PORT_AT_FULL_DUPLEX BIT2
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#define ETH_RX_FLOW_CTRL_DISABLED 0
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#define ETH_RX_FLOW_CTRL_ENBALED BIT3
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#define ETH_GMII_SPEED_100_10 0
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#define ETH_GMII_SPEED_1000 BIT4
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#define ETH_MII_SPEED_10 0
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#define ETH_MII_SPEED_100 BIT5
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#define ETH_NO_TX 0
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#define ETH_TX_IN_PROGRESS BIT7
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#define ETH_BYPASS_NO_ACTIVE 0
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#define ETH_BYPASS_ACTIVE BIT8
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#define ETH_PORT_NOT_AT_PARTITION_STATE 0
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#define ETH_PORT_AT_PARTITION_STATE BIT9
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#define ETH_PORT_TX_FIFO_NOT_EMPTY 0
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#define ETH_PORT_TX_FIFO_EMPTY BIT10
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#define ETH_DEFAULT_RX_BPDU_QUEUE_3 (BIT23 | BIT22)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_4 BIT24
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#define ETH_DEFAULT_RX_BPDU_QUEUE_5 (BIT24 | BIT22)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_6 (BIT24 | BIT23)
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#define ETH_DEFAULT_RX_BPDU_QUEUE_7 (BIT24 | BIT23 | BIT22)
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/* SMI reg */
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#define ETH_SMI_BUSY BIT28 /* 0 - Write, 1 - Read */
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#define ETH_SMI_READ_VALID BIT27 /* 0 - Write, 1 - Read */
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#define ETH_SMI_OPCODE_WRITE 0 /* Completion of Read operation */
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#define ETH_SMI_OPCODE_READ BIT26 /* Operation is in progress */
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/* SDMA command status fields macros */
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/* Tx & Rx descriptors status */
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#define ETH_ERROR_SUMMARY (BIT0)
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/* Tx & Rx descriptors command */
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#define ETH_BUFFER_OWNED_BY_DMA (BIT31)
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/* Tx descriptors status */
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#define ETH_LC_ERROR (0 )
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#define ETH_UR_ERROR (BIT1 )
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#define ETH_RL_ERROR (BIT2 )
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#define ETH_LLC_SNAP_FORMAT (BIT9 )
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/* Rx descriptors status */
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#define ETH_CRC_ERROR (0 )
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#define ETH_OVERRUN_ERROR (BIT1 )
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#define ETH_MAX_FRAME_LENGTH_ERROR (BIT2 )
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#define ETH_RESOURCE_ERROR ((BIT2 | BIT1))
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#define ETH_VLAN_TAGGED (BIT19)
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#define ETH_BPDU_FRAME (BIT20)
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#define ETH_TCP_FRAME_OVER_IP_V_4 (0 )
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#define ETH_UDP_FRAME_OVER_IP_V_4 (BIT21)
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#define ETH_OTHER_FRAME_TYPE (BIT22)
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#define ETH_LAYER_2_IS_ETH_V_2 (BIT23)
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#define ETH_FRAME_TYPE_IP_V_4 (BIT24)
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#define ETH_FRAME_HEADER_OK (BIT25)
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#define ETH_RX_LAST_DESC (BIT26)
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#define ETH_RX_FIRST_DESC (BIT27)
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#define ETH_UNKNOWN_DESTINATION_ADDR (BIT28)
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#define ETH_RX_ENABLE_INTERRUPT (BIT29)
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#define ETH_LAYER_4_CHECKSUM_OK (BIT30)
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/* Rx descriptors byte count */
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#define ETH_FRAME_FRAGMENTED (BIT2)
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/* Tx descriptors command */
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#define ETH_LAYER_4_CHECKSUM_FIRST_DESC (BIT10)
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#define ETH_FRAME_SET_TO_VLAN (BIT15)
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#define ETH_TCP_FRAME (0 )
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#define ETH_UDP_FRAME (BIT16)
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#define ETH_GEN_TCP_UDP_CHECKSUM (BIT17)
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#define ETH_GEN_IP_V_4_CHECKSUM (BIT18)
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#define ETH_ZERO_PADDING (BIT19)
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#define ETH_TX_LAST_DESC (BIT20)
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#define ETH_TX_FIRST_DESC (BIT21)
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#define ETH_GEN_CRC (BIT22)
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#define ETH_TX_ENABLE_INTERRUPT (BIT23)
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#define ETH_AUTO_MODE (BIT30)
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/* typedefs */
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typedef enum _eth_func_ret_status {
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ETH_OK, /* Returned as expected. */
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ETH_ERROR, /* Fundamental error. */
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ETH_RETRY, /* Could not process request. Try later.*/
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ETH_END_OF_JOB, /* Ring has nothing to process. */
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ETH_QUEUE_FULL, /* Ring resource error. */
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ETH_QUEUE_LAST_RESOURCE /* Ring resources about to exhaust. */
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} ETH_FUNC_RET_STATUS;
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typedef enum _eth_target {
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ETH_TARGET_DRAM,
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ETH_TARGET_DEVICE,
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ETH_TARGET_CBS,
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ETH_TARGET_PCI0,
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ETH_TARGET_PCI1
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} ETH_TARGET;
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/* These are for big-endian machines. Little endian needs different
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* definitions.
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*/
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#if defined(__BIG_ENDIAN)
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struct eth_rx_desc {
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u16 byte_cnt; /* Descriptor buffer byte count */
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u16 buf_size; /* Buffer size */
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u32 cmd_sts; /* Descriptor command status */
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u32 next_desc_ptr; /* Next descriptor pointer */
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u32 buf_ptr; /* Descriptor buffer pointer */
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};
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struct eth_tx_desc {
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u16 byte_cnt; /* buffer byte count */
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u16 l4i_chk; /* CPU provided TCP checksum */
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u32 cmd_sts; /* Command/status field */
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u32 next_desc_ptr; /* Pointer to next descriptor */
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u32 buf_ptr; /* pointer to buffer for this descriptor*/
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};
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#elif defined(__LITTLE_ENDIAN)
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struct eth_rx_desc {
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u32 cmd_sts; /* Descriptor command status */
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u16 buf_size; /* Buffer size */
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u16 byte_cnt; /* Descriptor buffer byte count */
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u32 buf_ptr; /* Descriptor buffer pointer */
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u32 next_desc_ptr; /* Next descriptor pointer */
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};
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struct eth_tx_desc {
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u32 cmd_sts; /* Command/status field */
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u16 l4i_chk; /* CPU provided TCP checksum */
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u16 byte_cnt; /* buffer byte count */
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u32 buf_ptr; /* pointer to buffer for this descriptor*/
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u32 next_desc_ptr; /* Pointer to next descriptor */
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};
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#else
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#error One of __BIG_ENDIAN or __LITTLE_ENDIAN must be defined
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#endif
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/* Unified struct for Rx and Tx operations. The user is not required to */
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/* be familier with neither Tx nor Rx descriptors. */
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struct pkt_info {
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unsigned short byte_cnt; /* Descriptor buffer byte count */
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unsigned short l4i_chk; /* Tx CPU provided TCP Checksum */
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unsigned int cmd_sts; /* Descriptor command status */
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dma_addr_t buf_ptr; /* Descriptor buffer pointer */
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struct sk_buff *return_info; /* User resource return information */
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};
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/* Ethernet port specific infomation */
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struct mv643xx_mib_counters {
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u64 good_octets_received;
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u32 bad_octets_received;
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u32 internal_mac_transmit_err;
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u32 good_frames_received;
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u32 bad_frames_received;
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u32 broadcast_frames_received;
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u32 multicast_frames_received;
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u32 frames_64_octets;
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u32 frames_65_to_127_octets;
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u32 frames_128_to_255_octets;
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u32 frames_256_to_511_octets;
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u32 frames_512_to_1023_octets;
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u32 frames_1024_to_max_octets;
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u64 good_octets_sent;
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u32 good_frames_sent;
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u32 excessive_collision;
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u32 multicast_frames_sent;
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u32 broadcast_frames_sent;
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u32 unrec_mac_control_received;
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u32 fc_sent;
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u32 good_fc_received;
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u32 bad_fc_received;
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u32 undersize_received;
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u32 fragments_received;
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u32 oversize_received;
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u32 jabber_received;
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u32 mac_receive_error;
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u32 bad_crc_event;
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u32 collision;
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u32 late_collision;
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};
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struct mv643xx_private {
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int port_num; /* User Ethernet port number */
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u8 port_mac_addr[6]; /* User defined port MAC address.*/
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u32 port_config; /* User port configuration value*/
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u32 port_config_extend; /* User port config extend value*/
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u32 port_sdma_config; /* User port SDMA config value */
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u32 port_serial_control; /* User port serial control value */
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u32 port_tx_queue_command; /* Port active Tx queues summary*/
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u32 port_rx_queue_command; /* Port active Rx queues summary*/
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u32 rx_sram_addr; /* Base address of rx sram area */
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u32 rx_sram_size; /* Size of rx sram area */
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u32 tx_sram_addr; /* Base address of tx sram area */
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u32 tx_sram_size; /* Size of tx sram area */
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int rx_resource_err; /* Rx ring resource error flag */
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int tx_resource_err; /* Tx ring resource error flag */
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/* Tx/Rx rings managment indexes fields. For driver use */
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/* Next available and first returning Rx resource */
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int rx_curr_desc_q, rx_used_desc_q;
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/* Next available and first returning Tx resource */
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int tx_curr_desc_q, tx_used_desc_q;
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#ifdef MV643XX_CHECKSUM_OFFLOAD_TX
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int tx_first_desc_q;
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u32 tx_first_command;
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#endif
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#ifdef MV643XX_TX_FAST_REFILL
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u32 tx_clean_threshold;
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#endif
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struct eth_rx_desc *p_rx_desc_area;
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dma_addr_t rx_desc_dma;
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unsigned int rx_desc_area_size;
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struct sk_buff **rx_skb;
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struct eth_tx_desc *p_tx_desc_area;
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dma_addr_t tx_desc_dma;
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unsigned int tx_desc_area_size;
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struct sk_buff **tx_skb;
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struct work_struct tx_timeout_task;
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/*
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* Former struct mv643xx_eth_priv members start here
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*/
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struct net_device_stats stats;
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struct mv643xx_mib_counters mib_counters;
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spinlock_t lock;
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/* Size of Tx Ring per queue */
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unsigned int tx_ring_size;
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/* Ammont of SKBs outstanding on Tx queue */
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unsigned int tx_ring_skbs;
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/* Size of Rx Ring per queue */
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unsigned int rx_ring_size;
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/* Ammount of SKBs allocated to Rx Ring per queue */
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unsigned int rx_ring_skbs;
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/*
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* rx_task used to fill RX ring out of bottom half context
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*/
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struct work_struct rx_task;
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/*
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* Used in case RX Ring is empty, which can be caused when
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* system does not have resources (skb's)
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*/
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struct timer_list timeout;
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long rx_task_busy __attribute__ ((aligned(SMP_CACHE_BYTES)));
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unsigned rx_timer_flag;
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u32 rx_int_coal;
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u32 tx_int_coal;
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};
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/* ethernet.h API list */
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/* Port operation control routines */
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static void eth_port_init(struct mv643xx_private *mp);
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static void eth_port_reset(unsigned int eth_port_num);
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static void eth_port_start(struct mv643xx_private *mp);
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static void ethernet_set_config_reg(unsigned int eth_port_num,
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unsigned int value);
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static unsigned int ethernet_get_config_reg(unsigned int eth_port_num);
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/* Port MAC address routines */
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static void eth_port_uc_addr_set(unsigned int eth_port_num,
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unsigned char *p_addr);
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/* PHY and MIB routines */
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static void ethernet_phy_reset(unsigned int eth_port_num);
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static void eth_port_write_smi_reg(unsigned int eth_port_num,
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unsigned int phy_reg, unsigned int value);
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static void eth_port_read_smi_reg(unsigned int eth_port_num,
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unsigned int phy_reg, unsigned int *value);
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static void eth_clear_mib_counters(unsigned int eth_port_num);
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/* Port data flow control routines */
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static ETH_FUNC_RET_STATUS eth_port_send(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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static ETH_FUNC_RET_STATUS eth_tx_return_desc(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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static ETH_FUNC_RET_STATUS eth_port_receive(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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static ETH_FUNC_RET_STATUS eth_rx_return_buff(struct mv643xx_private *mp,
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struct pkt_info *p_pkt_info);
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#endif /* __MV643XX_ETH_H__ */
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