0d1c38398f
With WL1271, the firmware version can only be read right after booting the chip. To keep WL1251 aligned with this procedure, the code that reads the firmware version initially has been moved to a common place where it can be read from both chipsets. Signed-off-by: Luciano Coelho <luciano.coelho@nokia.com> Signed-off-by: Kalle Valo <kalle.valo@nokia.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
298 lines
8.0 KiB
C
298 lines
8.0 KiB
C
/*
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* This file is part of wl12xx
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*
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* Copyright (C) 2008 Nokia Corporation
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*
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* Contact: Kalle Valo <kalle.valo@nokia.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/gpio.h>
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#include "reg.h"
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#include "boot.h"
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#include "spi.h"
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#include "event.h"
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static void wl12xx_boot_enable_interrupts(struct wl12xx *wl)
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{
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enable_irq(wl->irq);
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}
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void wl12xx_boot_target_enable_interrupts(struct wl12xx *wl)
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{
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wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_MASK, ~(wl->intr_mask));
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wl12xx_reg_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
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}
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int wl12xx_boot_soft_reset(struct wl12xx *wl)
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{
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unsigned long timeout;
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u32 boot_data;
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/* perform soft reset */
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wl12xx_reg_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
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/* SOFT_RESET is self clearing */
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timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
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while (1) {
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boot_data = wl12xx_reg_read32(wl, ACX_REG_SLV_SOFT_RESET);
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wl12xx_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
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if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
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break;
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if (time_after(jiffies, timeout)) {
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/* 1.2 check pWhalBus->uSelfClearTime if the
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* timeout was reached */
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wl12xx_error("soft reset timeout");
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return -1;
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}
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udelay(SOFT_RESET_STALL_TIME);
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}
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/* disable Rx/Tx */
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wl12xx_reg_write32(wl, ENABLE, 0x0);
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/* disable auto calibration on start*/
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wl12xx_reg_write32(wl, SPARE_A2, 0xffff);
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return 0;
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}
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int wl12xx_boot_init_seq(struct wl12xx *wl)
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{
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u32 scr_pad6, init_data, tmp, elp_cmd, ref_freq;
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/*
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* col #1: INTEGER_DIVIDER
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* col #2: FRACTIONAL_DIVIDER
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* col #3: ATTN_BB
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* col #4: ALPHA_BB
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* col #5: STOP_TIME_BB
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* col #6: BB_PLL_LOOP_FILTER
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*/
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static const u32 LUT[REF_FREQ_NUM][LUT_PARAM_NUM] = {
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{ 83, 87381, 0xB, 5, 0xF00, 3}, /* REF_FREQ_19_2*/
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{ 61, 141154, 0xB, 5, 0x1450, 2}, /* REF_FREQ_26_0*/
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{ 41, 174763, 0xC, 6, 0x2D00, 1}, /* REF_FREQ_38_4*/
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{ 40, 0, 0xC, 6, 0x2EE0, 1}, /* REF_FREQ_40_0*/
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{ 47, 162280, 0xC, 6, 0x2760, 1} /* REF_FREQ_33_6 */
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};
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/* read NVS params */
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scr_pad6 = wl12xx_reg_read32(wl, SCR_PAD6);
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wl12xx_debug(DEBUG_BOOT, "scr_pad6 0x%x", scr_pad6);
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/* read ELP_CMD */
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elp_cmd = wl12xx_reg_read32(wl, ELP_CMD);
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wl12xx_debug(DEBUG_BOOT, "elp_cmd 0x%x", elp_cmd);
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/* set the BB calibration time to be 300 usec (PLL_CAL_TIME) */
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ref_freq = scr_pad6 & 0x000000FF;
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wl12xx_debug(DEBUG_BOOT, "ref_freq 0x%x", ref_freq);
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wl12xx_reg_write32(wl, PLL_CAL_TIME, 0x9);
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/*
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* PG 1.2: set the clock buffer time to be 210 usec (CLK_BUF_TIME)
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*/
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wl12xx_reg_write32(wl, CLK_BUF_TIME, 0x6);
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/*
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* set the clock detect feature to work in the restart wu procedure
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* (ELP_CFG_MODE[14]) and Select the clock source type
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* (ELP_CFG_MODE[13:12])
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*/
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tmp = ((scr_pad6 & 0x0000FF00) << 4) | 0x00004000;
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wl12xx_reg_write32(wl, ELP_CFG_MODE, tmp);
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/* PG 1.2: enable the BB PLL fix. Enable the PLL_LIMP_CLK_EN_CMD */
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elp_cmd |= 0x00000040;
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wl12xx_reg_write32(wl, ELP_CMD, elp_cmd);
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/* PG 1.2: Set the BB PLL stable time to be 1000usec
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* (PLL_STABLE_TIME) */
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wl12xx_reg_write32(wl, CFG_PLL_SYNC_CNT, 0x20);
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/* PG 1.2: read clock request time */
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init_data = wl12xx_reg_read32(wl, CLK_REQ_TIME);
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/*
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* PG 1.2: set the clock request time to be ref_clk_settling_time -
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* 1ms = 4ms
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*/
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if (init_data > 0x21)
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tmp = init_data - 0x21;
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else
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tmp = 0;
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wl12xx_reg_write32(wl, CLK_REQ_TIME, tmp);
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/* set BB PLL configurations in RF AFE */
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wl12xx_reg_write32(wl, 0x003058cc, 0x4B5);
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/* set RF_AFE_REG_5 */
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wl12xx_reg_write32(wl, 0x003058d4, 0x50);
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/* set RF_AFE_CTRL_REG_2 */
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wl12xx_reg_write32(wl, 0x00305948, 0x11c001);
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/*
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* change RF PLL and BB PLL divider for VCO clock and adjust VCO
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* bais current(RF_AFE_REG_13)
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*/
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wl12xx_reg_write32(wl, 0x003058f4, 0x1e);
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/* set BB PLL configurations */
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tmp = LUT[ref_freq][LUT_PARAM_INTEGER_DIVIDER] | 0x00017000;
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wl12xx_reg_write32(wl, 0x00305840, tmp);
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/* set fractional divider according to Appendix C-BB PLL
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* Calculations
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*/
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tmp = LUT[ref_freq][LUT_PARAM_FRACTIONAL_DIVIDER];
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wl12xx_reg_write32(wl, 0x00305844, tmp);
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/* set the initial data for the sigma delta */
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wl12xx_reg_write32(wl, 0x00305848, 0x3039);
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/*
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* set the accumulator attenuation value, calibration loop1
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* (alpha), calibration loop2 (beta), calibration loop3 (gamma) and
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* the VCO gain
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*/
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tmp = (LUT[ref_freq][LUT_PARAM_ATTN_BB] << 16) |
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(LUT[ref_freq][LUT_PARAM_ALPHA_BB] << 12) | 0x1;
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wl12xx_reg_write32(wl, 0x00305854, tmp);
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/*
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* set the calibration stop time after holdoff time expires and set
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* settling time HOLD_OFF_TIME_BB
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*/
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tmp = LUT[ref_freq][LUT_PARAM_STOP_TIME_BB] | 0x000A0000;
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wl12xx_reg_write32(wl, 0x00305858, tmp);
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/*
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* set BB PLL Loop filter capacitor3- BB_C3[2:0] and set BB PLL
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* constant leakage current to linearize PFD to 0uA -
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* BB_ILOOPF[7:3]
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*/
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tmp = LUT[ref_freq][LUT_PARAM_BB_PLL_LOOP_FILTER] | 0x00000030;
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wl12xx_reg_write32(wl, 0x003058f8, tmp);
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/*
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* set regulator output voltage for n divider to
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* 1.35-BB_REFDIV[1:0], set charge pump current- BB_CPGAIN[4:2],
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* set BB PLL Loop filter capacitor2- BB_C2[7:5], set gain of BB
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* PLL auto-call to normal mode- BB_CALGAIN_3DB[8]
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*/
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wl12xx_reg_write32(wl, 0x003058f0, 0x29);
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/* enable restart wakeup sequence (ELP_CMD[0]) */
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wl12xx_reg_write32(wl, ELP_CMD, elp_cmd | 0x1);
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/* restart sequence completed */
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udelay(2000);
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return 0;
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}
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int wl12xx_boot_run_firmware(struct wl12xx *wl)
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{
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int loop, ret;
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u32 chip_id, interrupt;
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wl->chip.op_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
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chip_id = wl12xx_reg_read32(wl, CHIP_ID_B);
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wl12xx_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
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if (chip_id != wl->chip.id) {
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wl12xx_error("chip id doesn't match after firmware boot");
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return -EIO;
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}
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/* wait for init to complete */
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loop = 0;
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while (loop++ < INIT_LOOP) {
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udelay(INIT_LOOP_DELAY);
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interrupt = wl12xx_reg_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
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if (interrupt == 0xffffffff) {
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wl12xx_error("error reading hardware complete "
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"init indication");
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return -EIO;
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}
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/* check that ACX_INTR_INIT_COMPLETE is enabled */
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else if (interrupt & wl->chip.intr_init_complete) {
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wl12xx_reg_write32(wl, ACX_REG_INTERRUPT_ACK,
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wl->chip.intr_init_complete);
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break;
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}
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}
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if (loop >= INIT_LOOP) {
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wl12xx_error("timeout waiting for the hardware to "
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"complete initialization");
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return -EIO;
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}
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/* get hardware config command mail box */
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wl->cmd_box_addr = wl12xx_reg_read32(wl, REG_COMMAND_MAILBOX_PTR);
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/* get hardware config event mail box */
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wl->event_box_addr = wl12xx_reg_read32(wl, REG_EVENT_MAILBOX_PTR);
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/* set the working partition to its "running" mode offset */
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wl12xx_set_partition(wl,
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wl->chip.p_table[PART_WORK].mem.start,
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wl->chip.p_table[PART_WORK].mem.size,
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wl->chip.p_table[PART_WORK].reg.start,
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wl->chip.p_table[PART_WORK].reg.size);
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wl12xx_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
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wl->cmd_box_addr, wl->event_box_addr);
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wl->chip.op_fw_version(wl);
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/*
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* in case of full asynchronous mode the firmware event must be
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* ready to receive event from the command mailbox
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*/
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/* enable gpio interrupts */
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wl12xx_boot_enable_interrupts(wl);
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wl->chip.op_target_enable_interrupts(wl);
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/* unmask all mbox events */
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wl->event_mask = 0xffffffff;
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ret = wl12xx_event_unmask(wl);
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if (ret < 0) {
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wl12xx_error("EVENT mask setting failed");
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return ret;
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}
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wl12xx_event_mbox_config(wl);
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/* firmware startup completed */
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return 0;
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}
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