d1bef4ed5f
This patch-queue improves the generic IRQ layer to be truly generic, by adding various abstractions and features to it, without impacting existing functionality. While the queue can be best described as "fix and improve everything in the generic IRQ layer that we could think of", and thus it consists of many smaller features and lots of cleanups, the one feature that stands out most is the new 'irq chip' abstraction. The irq-chip abstraction is about describing and coding and IRQ controller driver by mapping its raw hardware capabilities [and quirks, if needed] in a straightforward way, without having to think about "IRQ flow" (level/edge/etc.) type of details. This stands in contrast with the current 'irq-type' model of genirq architectures, which 'mixes' raw hardware capabilities with 'flow' details. The patchset supports both types of irq controller designs at once, and converts i386 and x86_64 to the new irq-chip design. As a bonus side-effect of the irq-chip approach, chained interrupt controllers (master/slave PIC constructs, etc.) are now supported by design as well. The end result of this patchset intends to be simpler architecture-level code and more consolidation between architectures. We reused many bits of code and many concepts from Russell King's ARM IRQ layer, the merging of which was one of the motivations for this patchset. This patch: rename desc->handler to desc->chip. Originally i did not want to do this, because it's a big patch. But having both "desc->handler", "desc->handle_irq" and "action->handler" caused a large degree of confusion and made the code appear alot less clean than it truly is. I have also attempted a dual approach as well by introducing a desc->chip alias - but that just wasnt robust enough and broke frequently. So lets get over with this quickly. The conversion was done automatically via scripts and converts all the code in the kernel. This renaming patch is the first one amongst the patches, so that the remaining patches can stay flexible and can be merged and split up without having some big monolithic patch act as a merge barrier. [akpm@osdl.org: build fix] [akpm@osdl.org: another build fix] Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
154 lines
3.9 KiB
C
154 lines
3.9 KiB
C
/*
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* Interrupt controller driver for Xilinx Virtex-II Pro.
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*
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* Author: MontaVista Software, Inc.
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* source@mvista.com
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*
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* 2002-2004 (c) MontaVista Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <asm/io.h>
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#include <platforms/4xx/xparameters/xparameters.h>
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#include <asm/ibm4xx.h>
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#include <asm/machdep.h>
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/* No one else should require these constants, so define them locally here. */
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#define ISR 0 /* Interrupt Status Register */
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#define IPR 1 /* Interrupt Pending Register */
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#define IER 2 /* Interrupt Enable Register */
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#define IAR 3 /* Interrupt Acknowledge Register */
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#define SIE 4 /* Set Interrupt Enable bits */
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#define CIE 5 /* Clear Interrupt Enable bits */
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#define IVR 6 /* Interrupt Vector Register */
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#define MER 7 /* Master Enable Register */
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#if XPAR_XINTC_USE_DCR == 0
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static volatile u32 *intc;
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#define intc_out_be32(addr, mask) out_be32((addr), (mask))
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#define intc_in_be32(addr) in_be32((addr))
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#else
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#define intc XPAR_INTC_0_BASEADDR
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#define intc_out_be32(addr, mask) mtdcr((addr), (mask))
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#define intc_in_be32(addr) mfdcr((addr))
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#endif
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static void
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xilinx_intc_enable(unsigned int irq)
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{
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unsigned long mask = (0x00000001 << (irq & 31));
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pr_debug("enable: %d\n", irq);
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intc_out_be32(intc + SIE, mask);
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}
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static void
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xilinx_intc_disable(unsigned int irq)
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{
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unsigned long mask = (0x00000001 << (irq & 31));
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pr_debug("disable: %d\n", irq);
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intc_out_be32(intc + CIE, mask);
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}
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static void
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xilinx_intc_disable_and_ack(unsigned int irq)
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{
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unsigned long mask = (0x00000001 << (irq & 31));
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pr_debug("disable_and_ack: %d\n", irq);
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intc_out_be32(intc + CIE, mask);
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if (!(irq_desc[irq].status & IRQ_LEVEL))
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intc_out_be32(intc + IAR, mask); /* ack edge triggered intr */
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}
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static void
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xilinx_intc_end(unsigned int irq)
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{
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unsigned long mask = (0x00000001 << (irq & 31));
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pr_debug("end: %d\n", irq);
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
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intc_out_be32(intc + SIE, mask);
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/* ack level sensitive intr */
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if (irq_desc[irq].status & IRQ_LEVEL)
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intc_out_be32(intc + IAR, mask);
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}
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}
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static struct hw_interrupt_type xilinx_intc = {
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.typename = "Xilinx Interrupt Controller",
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.enable = xilinx_intc_enable,
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.disable = xilinx_intc_disable,
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.ack = xilinx_intc_disable_and_ack,
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.end = xilinx_intc_end,
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};
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int
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xilinx_pic_get_irq(struct pt_regs *regs)
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{
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int irq;
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/*
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* NOTE: This function is the one that needs to be improved in
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* order to handle multiple interrupt controllers. It currently
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* is hardcoded to check for interrupts only on the first INTC.
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*/
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irq = intc_in_be32(intc + IVR);
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if (irq != -1)
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irq = irq;
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pr_debug("get_irq: %d\n", irq);
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return (irq);
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}
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void __init
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ppc4xx_pic_init(void)
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{
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int i;
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/*
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* NOTE: The assumption here is that NR_IRQS is 32 or less
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* (NR_IRQS is 32 for PowerPC 405 cores by default).
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*/
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#if (NR_IRQS > 32)
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#error NR_IRQS > 32 not supported
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#endif
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#if XPAR_XINTC_USE_DCR == 0
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intc = ioremap(XPAR_INTC_0_BASEADDR, 32);
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printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX mapped to 0x%08lX\n",
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(unsigned long) XPAR_INTC_0_BASEADDR, (unsigned long) intc);
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#else
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printk(KERN_INFO "Xilinx INTC #0 at 0x%08lX (DCR)\n",
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(unsigned long) XPAR_INTC_0_BASEADDR);
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#endif
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/*
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* Disable all external interrupts until they are
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* explicity requested.
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*/
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intc_out_be32(intc + IER, 0);
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/* Acknowledge any pending interrupts just in case. */
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intc_out_be32(intc + IAR, ~(u32) 0);
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/* Turn on the Master Enable. */
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intc_out_be32(intc + MER, 0x3UL);
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ppc_md.get_irq = xilinx_pic_get_irq;
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for (i = 0; i < NR_IRQS; ++i) {
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irq_desc[i].chip = &xilinx_intc;
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if (XPAR_INTC_0_KIND_OF_INTR & (0x00000001 << i))
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irq_desc[i].status &= ~IRQ_LEVEL;
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else
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irq_desc[i].status |= IRQ_LEVEL;
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}
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}
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