7282bee787
The attached patches provides part 8 of an architecture implementation for the Tensilica Xtensa CPU series. Signed-off-by: Chris Zankel <chris@zankel.net> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
30 lines
613 B
C
30 lines
613 B
C
/*
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* include/asm-xtensa/platform-iss/hardware.h
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2001 Tensilica Inc.
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*/
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/*
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* This file contains the default configuration of ISS.
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*/
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#ifndef __ASM_XTENSA_ISS_HARDWARE
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#define __ASM_XTENSA_ISS_HARDWARE
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/*
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* Memory configuration.
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*/
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#define PLATFORM_DEFAULT_MEM_START XSHAL_RAM_PADDR
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#define PLATFORM_DEFAULT_MEM_SIZE XSHAL_RAM_VSIZE
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/*
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* Interrupt configuration.
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*/
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#endif /* __ASM_XTENSA_ISS_HARDWARE */
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