9b6d351a75
DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files that
don't require corresponding C changes any more, which is indicating that
the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over to fully
support the platform with DT.
* Renesas platforms continue their conversion over from legacy platform devices
to DT-based for hardware description.
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Merge tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC DT updates from Olof Johansson:
"DT and DT-conversion-related changes for various ARM platforms. Most
of these are to enable various devices on various boards, etc, and not
necessarily worth enumerating.
New boards and systems continue to come in as new devicetree files
that don't require corresponding C changes any more, which is
indicating that the system is starting to work fairly well.
A few things worth pointing out:
* ST Ericsson ux500 platforms have made the major push to move over
to fully support the platform with DT
* Renesas platforms continue their conversion over from legacy
platform devices to DT-based for hardware description"
* tag 'dt-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (327 commits)
ARM: dts: SiRF: add pin group for USP0 with only RX or TX frame sync
ARM: dts: SiRF: add lost usp1_uart_nostreamctrl pin group for atlas6
ARM: dts: sirf: add lost minigpsrtc device node
ARM: dts: sirf: add clock, frequence-voltage table for CPU0
ARM: dts: sirf: add lost bus_width, clock and status for sdhci
ARM: dts: sirf: add lost clocks for cphifbg
ARM: dts: socfpga: add pl330 clock
ARM: dts: socfpga: update L2 tag and data latency
arm: sun7i: cubietruck: Enable the i2c controllers
ARM: dts: add support for EXYNOS4412 based TINY4412 board
ARM: dts: Add initial support for Arndale Octa board
ARM: bcm2835: add USB controller to device tree
ARM: dts: MSM8974: Add MMIO architected timer node
ARM: dts: MSM8974: Add restart node
ARM: dts: sun7i: external clock outputs
ARM: dts: sun7i: Change 32768 Hz oscillator node name to clk@N style
ARM: dts: sun7i: Add pin muxing options for clock outputs
ARM: dts: sun7i: Add rtp controller node
ARM: dts: sun5i: Add rtp controller node
ARM: dts: sun4i: Add rtp controller node
...
339 lines
13 KiB
C
339 lines
13 KiB
C
/*
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* r8a7778 clock framework support
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*
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* Copyright (C) 2013 Renesas Solutions Corp.
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* Copyright (C) 2013 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
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*
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* based on r8a7779
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*
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* Copyright (C) 2011 Renesas Solutions Corp.
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* Copyright (C) 2011 Magnus Damm
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* MD MD MD MD PLLA PLLB EXTAL clki clkz
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* 19 18 12 11 (HMz) (MHz) (MHz)
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*----------------------------------------------------------------------------
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* 1 0 0 0 x21 x21 38.00 800 800
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* 1 0 0 1 x24 x24 33.33 800 800
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* 1 0 1 0 x28 x28 28.50 800 800
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* 1 0 1 1 x32 x32 25.00 800 800
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* 1 1 0 1 x24 x21 33.33 800 700
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* 1 1 1 0 x28 x21 28.50 800 600
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* 1 1 1 1 x32 x24 25.00 800 600
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*/
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#include <linux/io.h>
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#include <linux/sh_clk.h>
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#include <linux/clkdev.h>
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#include <mach/clock.h>
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#include <mach/common.h>
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#define MSTPCR0 IOMEM(0xffc80030)
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#define MSTPCR1 IOMEM(0xffc80034)
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#define MSTPCR3 IOMEM(0xffc8003c)
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#define MSTPSR1 IOMEM(0xffc80044)
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#define MSTPSR4 IOMEM(0xffc80048)
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#define MSTPSR6 IOMEM(0xffc8004c)
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#define MSTPCR4 IOMEM(0xffc80050)
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#define MSTPCR5 IOMEM(0xffc80054)
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#define MSTPCR6 IOMEM(0xffc80058)
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#define MODEMR 0xFFCC0020
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#define MD(nr) BIT(nr)
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/* ioremap() through clock mapping mandatory to avoid
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* collision with ARM coherent DMA virtual memory range.
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*/
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static struct clk_mapping cpg_mapping = {
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.phys = 0xffc80000,
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.len = 0x80,
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};
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static struct clk extal_clk = {
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/* .rate will be updated on r8a7778_clock_init() */
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.mapping = &cpg_mapping,
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};
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static struct clk audio_clk_a = {
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};
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static struct clk audio_clk_b = {
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};
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static struct clk audio_clk_c = {
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};
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/*
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* clock ratio of these clock will be updated
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* on r8a7778_clock_init()
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*/
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SH_FIXED_RATIO_CLK_SET(plla_clk, extal_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(pllb_clk, extal_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(i_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s1_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s3_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(s4_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(b_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(out_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(p_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(g_clk, plla_clk, 1, 1);
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SH_FIXED_RATIO_CLK_SET(z_clk, pllb_clk, 1, 1);
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static struct clk *main_clks[] = {
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&extal_clk,
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&plla_clk,
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&pllb_clk,
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&i_clk,
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&s_clk,
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&s1_clk,
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&s3_clk,
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&s4_clk,
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&b_clk,
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&out_clk,
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&p_clk,
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&g_clk,
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&z_clk,
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&audio_clk_a,
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&audio_clk_b,
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&audio_clk_c,
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};
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enum {
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MSTP531, MSTP530,
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MSTP529, MSTP528, MSTP527, MSTP526, MSTP525, MSTP524, MSTP523,
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MSTP331,
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MSTP323, MSTP322, MSTP321,
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MSTP311, MSTP310,
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MSTP309, MSTP308, MSTP307,
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MSTP114,
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MSTP110, MSTP109,
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MSTP100,
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MSTP030,
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MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
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MSTP016, MSTP015, MSTP012, MSTP011, MSTP010,
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MSTP009, MSTP008, MSTP007,
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MSTP_NR };
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP531] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 31, 0), /* SCU0 */
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[MSTP530] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 30, 0), /* SCU1 */
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[MSTP529] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 29, 0), /* SCU2 */
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[MSTP528] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 28, 0), /* SCU3 */
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[MSTP527] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 27, 0), /* SCU4 */
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[MSTP526] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 26, 0), /* SCU5 */
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[MSTP525] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 25, 0), /* SCU6 */
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[MSTP524] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 24, 0), /* SCU7 */
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[MSTP523] = SH_CLK_MSTP32(&p_clk, MSTPCR5, 23, 0), /* SCU8 */
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[MSTP331] = SH_CLK_MSTP32(&s4_clk, MSTPCR3, 31, 0), /* MMC */
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[MSTP323] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 23, 0), /* SDHI0 */
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[MSTP322] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 22, 0), /* SDHI1 */
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[MSTP321] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 21, 0), /* SDHI2 */
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[MSTP311] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 11, 0), /* SSI4 */
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[MSTP310] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 10, 0), /* SSI5 */
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[MSTP309] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 9, 0), /* SSI6 */
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[MSTP308] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 8, 0), /* SSI7 */
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[MSTP307] = SH_CLK_MSTP32(&p_clk, MSTPCR3, 7, 0), /* SSI8 */
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[MSTP114] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 14, 0), /* Ether */
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[MSTP110] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 10, 0), /* VIN0 */
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[MSTP109] = SH_CLK_MSTP32(&s_clk, MSTPCR1, 9, 0), /* VIN1 */
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[MSTP100] = SH_CLK_MSTP32(&p_clk, MSTPCR1, 0, 0), /* USB0/1 */
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[MSTP030] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 30, 0), /* I2C0 */
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[MSTP029] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 29, 0), /* I2C1 */
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[MSTP028] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 28, 0), /* I2C2 */
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[MSTP027] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 27, 0), /* I2C3 */
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[MSTP026] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 26, 0), /* SCIF0 */
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[MSTP025] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 25, 0), /* SCIF1 */
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[MSTP024] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 24, 0), /* SCIF2 */
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[MSTP023] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 23, 0), /* SCIF3 */
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[MSTP022] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 22, 0), /* SCIF4 */
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[MSTP021] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 21, 0), /* SCIF5 */
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[MSTP016] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 16, 0), /* TMU0 */
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[MSTP015] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 15, 0), /* TMU1 */
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[MSTP012] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 12, 0), /* SSI0 */
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[MSTP011] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 11, 0), /* SSI1 */
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[MSTP010] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 10, 0), /* SSI2 */
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[MSTP009] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 9, 0), /* SSI3 */
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[MSTP008] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 8, 0), /* SRU */
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[MSTP007] = SH_CLK_MSTP32(&p_clk, MSTPCR0, 7, 0), /* HSPI */
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};
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static struct clk_lookup lookups[] = {
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/* main */
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CLKDEV_CON_ID("audio_clk_a", &audio_clk_a),
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CLKDEV_CON_ID("audio_clk_b", &audio_clk_b),
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CLKDEV_CON_ID("audio_clk_c", &audio_clk_c),
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CLKDEV_CON_ID("audio_clk_internal", &s1_clk),
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CLKDEV_CON_ID("shyway_clk", &s_clk),
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CLKDEV_CON_ID("peripheral_clk", &p_clk),
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/* MSTP32 clocks */
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CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP331]), /* MMC */
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CLKDEV_DEV_ID("ffe4e000.mmc", &mstp_clks[MSTP331]), /* MMC */
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CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
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CLKDEV_DEV_ID("ffe4c000.sd", &mstp_clks[MSTP323]), /* SDHI0 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
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CLKDEV_DEV_ID("ffe4d000.sd", &mstp_clks[MSTP322]), /* SDHI1 */
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
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CLKDEV_DEV_ID("ffe4f000.sd", &mstp_clks[MSTP321]), /* SDHI2 */
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CLKDEV_DEV_ID("r8a777x-ether", &mstp_clks[MSTP114]), /* Ether */
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CLKDEV_DEV_ID("r8a7778-vin.0", &mstp_clks[MSTP110]), /* VIN0 */
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CLKDEV_DEV_ID("r8a7778-vin.1", &mstp_clks[MSTP109]), /* VIN1 */
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CLKDEV_DEV_ID("ehci-platform", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
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CLKDEV_DEV_ID("ohci-platform", &mstp_clks[MSTP100]), /* USB OHCI port0/1 */
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CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP100]), /* USB FUNC */
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CLKDEV_DEV_ID("i2c-rcar.0", &mstp_clks[MSTP030]), /* I2C0 */
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CLKDEV_DEV_ID("ffc70000.i2c", &mstp_clks[MSTP030]), /* I2C0 */
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CLKDEV_DEV_ID("i2c-rcar.1", &mstp_clks[MSTP029]), /* I2C1 */
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CLKDEV_DEV_ID("ffc71000.i2c", &mstp_clks[MSTP029]), /* I2C1 */
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CLKDEV_DEV_ID("i2c-rcar.2", &mstp_clks[MSTP028]), /* I2C2 */
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CLKDEV_DEV_ID("ffc72000.i2c", &mstp_clks[MSTP028]), /* I2C2 */
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CLKDEV_DEV_ID("i2c-rcar.3", &mstp_clks[MSTP027]), /* I2C3 */
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CLKDEV_DEV_ID("ffc73000.i2c", &mstp_clks[MSTP027]), /* I2C3 */
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CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP026]), /* SCIF0 */
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CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP025]), /* SCIF1 */
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CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP024]), /* SCIF2 */
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CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
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CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
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CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
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CLKDEV_DEV_ID("sh_tmu.0", &mstp_clks[MSTP016]), /* TMU00 */
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CLKDEV_DEV_ID("sh_tmu.1", &mstp_clks[MSTP015]), /* TMU01 */
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CLKDEV_DEV_ID("sh-hspi.0", &mstp_clks[MSTP007]), /* HSPI0 */
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CLKDEV_DEV_ID("fffc7000.spi", &mstp_clks[MSTP007]), /* HSPI0 */
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CLKDEV_DEV_ID("sh-hspi.1", &mstp_clks[MSTP007]), /* HSPI1 */
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CLKDEV_DEV_ID("fffc8000.spi", &mstp_clks[MSTP007]), /* HSPI1 */
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CLKDEV_DEV_ID("sh-hspi.2", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("fffc6000.spi", &mstp_clks[MSTP007]), /* HSPI2 */
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CLKDEV_DEV_ID("rcar_sound", &mstp_clks[MSTP008]), /* SRU */
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CLKDEV_ICK_ID("ssi.0", "rcar_sound", &mstp_clks[MSTP012]),
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CLKDEV_ICK_ID("ssi.1", "rcar_sound", &mstp_clks[MSTP011]),
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CLKDEV_ICK_ID("ssi.2", "rcar_sound", &mstp_clks[MSTP010]),
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CLKDEV_ICK_ID("ssi.3", "rcar_sound", &mstp_clks[MSTP009]),
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CLKDEV_ICK_ID("ssi.4", "rcar_sound", &mstp_clks[MSTP311]),
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CLKDEV_ICK_ID("ssi.5", "rcar_sound", &mstp_clks[MSTP310]),
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CLKDEV_ICK_ID("ssi.6", "rcar_sound", &mstp_clks[MSTP309]),
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CLKDEV_ICK_ID("ssi.7", "rcar_sound", &mstp_clks[MSTP308]),
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CLKDEV_ICK_ID("ssi.8", "rcar_sound", &mstp_clks[MSTP307]),
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CLKDEV_ICK_ID("scu.0", "rcar_sound", &mstp_clks[MSTP531]),
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CLKDEV_ICK_ID("scu.1", "rcar_sound", &mstp_clks[MSTP530]),
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CLKDEV_ICK_ID("scu.2", "rcar_sound", &mstp_clks[MSTP529]),
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CLKDEV_ICK_ID("scu.3", "rcar_sound", &mstp_clks[MSTP528]),
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CLKDEV_ICK_ID("scu.4", "rcar_sound", &mstp_clks[MSTP527]),
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CLKDEV_ICK_ID("scu.5", "rcar_sound", &mstp_clks[MSTP526]),
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CLKDEV_ICK_ID("scu.6", "rcar_sound", &mstp_clks[MSTP525]),
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CLKDEV_ICK_ID("scu.7", "rcar_sound", &mstp_clks[MSTP524]),
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CLKDEV_ICK_ID("scu.8", "rcar_sound", &mstp_clks[MSTP523]),
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};
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void __init r8a7778_clock_init(void)
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{
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void __iomem *modemr = ioremap_nocache(MODEMR, PAGE_SIZE);
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u32 mode;
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int k, ret = 0;
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BUG_ON(!modemr);
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mode = ioread32(modemr);
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iounmap(modemr);
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switch (mode & (MD(19) | MD(18) | MD(12) | MD(11))) {
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case MD(19):
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extal_clk.rate = 38000000;
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SH_CLK_SET_RATIO(&plla_clk_ratio, 21, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
|
|
break;
|
|
case MD(19) | MD(11):
|
|
extal_clk.rate = 33333333;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
|
|
break;
|
|
case MD(19) | MD(12):
|
|
extal_clk.rate = 28500000;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 28, 1);
|
|
break;
|
|
case MD(19) | MD(12) | MD(11):
|
|
extal_clk.rate = 25000000;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 32, 1);
|
|
break;
|
|
case MD(19) | MD(18) | MD(11):
|
|
extal_clk.rate = 33333333;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 24, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
|
|
break;
|
|
case MD(19) | MD(18) | MD(12):
|
|
extal_clk.rate = 28500000;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 28, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 21, 1);
|
|
break;
|
|
case MD(19) | MD(18) | MD(12) | MD(11):
|
|
extal_clk.rate = 25000000;
|
|
SH_CLK_SET_RATIO(&plla_clk_ratio, 32, 1);
|
|
SH_CLK_SET_RATIO(&pllb_clk_ratio, 24, 1);
|
|
break;
|
|
default:
|
|
BUG();
|
|
}
|
|
|
|
if (mode & MD(1)) {
|
|
SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
|
|
SH_CLK_SET_RATIO(&s_clk_ratio, 1, 3);
|
|
SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 6);
|
|
SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
|
|
SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
|
|
SH_CLK_SET_RATIO(&p_clk_ratio, 1, 12);
|
|
SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
|
|
if (mode & MD(2)) {
|
|
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 18);
|
|
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 18);
|
|
} else {
|
|
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
|
|
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
|
|
}
|
|
} else {
|
|
SH_CLK_SET_RATIO(&i_clk_ratio, 1, 1);
|
|
SH_CLK_SET_RATIO(&s_clk_ratio, 1, 4);
|
|
SH_CLK_SET_RATIO(&s1_clk_ratio, 1, 8);
|
|
SH_CLK_SET_RATIO(&s3_clk_ratio, 1, 4);
|
|
SH_CLK_SET_RATIO(&s4_clk_ratio, 1, 8);
|
|
SH_CLK_SET_RATIO(&p_clk_ratio, 1, 16);
|
|
SH_CLK_SET_RATIO(&g_clk_ratio, 1, 12);
|
|
if (mode & MD(2)) {
|
|
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 16);
|
|
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 16);
|
|
} else {
|
|
SH_CLK_SET_RATIO(&b_clk_ratio, 1, 12);
|
|
SH_CLK_SET_RATIO(&out_clk_ratio, 1, 12);
|
|
}
|
|
}
|
|
|
|
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
|
|
ret = clk_register(main_clks[k]);
|
|
|
|
if (!ret)
|
|
ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
|
|
|
|
clkdev_add_table(lookups, ARRAY_SIZE(lookups));
|
|
|
|
if (!ret)
|
|
shmobile_clk_init();
|
|
else
|
|
panic("failed to setup r8a7778 clocks\n");
|
|
}
|