3a8954e8f2
Commit 9c1390a923ddb6fba1cf9d7440743369140c6d8a replaced all u_int's with u32 and u_long's with u64. Unfortunately, a u_long is still only 32-bits so they should have been replaced with u32 also. This can be verified by the register definitions in dt3155_io.h. It specifically states that the memory mapped registers are 32-bit. Fix this by changing all the u64 to u32. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Cc: Greg Kroah-Hartman <greg@kroah.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
359 lines
7.6 KiB
C
359 lines
7.6 KiB
C
/*
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Copyright 1996,2002 Gregory D. Hager, Alfred A. Rizzi, Noah J. Cowan,
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Jason Lapenta, Scott Smedley
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This file is part of the DT3155 Device Driver.
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The DT3155 Device Driver is free software; you can redistribute it
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and/or modify it under the terms of the GNU General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The DT3155 Device Driver is distributed in the hope that it will be
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useful, but WITHOUT ANY WARRANTY; without even the implied warranty
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of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with the DT3155 Device Driver; if not, write to the Free
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Software Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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MA 02111-1307 USA
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-- Changes --
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Date Programmer Description of changes made
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-------------------------------------------------------------------
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24-Jul-2002 SS GPL licence.
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*/
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/* This code is a modified version of examples provided by Data Translations.*/
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#ifndef DT3155_IO_INC
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#define DT3155_IO_INC
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/* macros to access registers */
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#define WriteMReg(Address, Data) (*((u32 *)(Address)) = Data)
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#define ReadMReg(Address, Data) (Data = *((u32 *)(Address)))
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/***************** 32 bit register globals **************/
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/* offsets for 32-bit memory mapped registers */
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#define EVEN_DMA_START 0x000
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#define ODD_DMA_START 0x00C
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#define EVEN_DMA_STRIDE 0x018
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#define ODD_DMA_STRIDE 0x024
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#define EVEN_PIXEL_FMT 0x030
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#define ODD_PIXEL_FMT 0x034
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#define FIFO_TRIGGER 0x038
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#define XFER_MODE 0x03C
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#define CSR1 0x040
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#define RETRY_WAIT_CNT 0x044
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#define INT_CSR 0x048
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#define EVEN_FLD_MASK 0x04C
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#define ODD_FLD_MASK 0x050
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#define MASK_LENGTH 0x054
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#define FIFO_FLAG_CNT 0x058
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#define IIC_CLK_DUR 0x05C
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#define IIC_CSR1 0x060
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#define IIC_CSR2 0x064
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#define EVEN_DMA_UPPR_LMT 0x08C
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#define ODD_DMA_UPPR_LMT 0x090
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#define CLK_DUR_VAL 0x01010101
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/******** Assignments and Typedefs for 32 bit Memory Mapped Registers ********/
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typedef union fifo_trigger_tag {
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u32 reg;
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struct {
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u32 PACKED:6;
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u32 :9;
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u32 PLANER:7;
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u32 :9;
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} fld;
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} FIFO_TRIGGER_R;
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typedef union xfer_mode_tag {
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u32 reg;
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struct {
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u32 :2;
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u32 FIELD_TOGGLE:1;
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u32 :5;
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u32 :2;
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u32 :22;
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} fld;
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} XFER_MODE_R;
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typedef union csr1_tag {
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u32 reg;
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struct {
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u32 CAP_CONT_EVE:1;
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u32 CAP_CONT_ODD:1;
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u32 CAP_SNGL_EVE:1;
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u32 CAP_SNGL_ODD:1;
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u32 FLD_DN_EVE :1;
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u32 FLD_DN_ODD :1;
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u32 SRST :1;
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u32 FIFO_EN :1;
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u32 FLD_CRPT_EVE:1;
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u32 FLD_CRPT_ODD:1;
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u32 ADDR_ERR_EVE:1;
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u32 ADDR_ERR_ODD:1;
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u32 CRPT_DIS :1;
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u32 RANGE_EN :1;
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u32 :16;
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} fld;
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} CSR1_R;
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typedef union retry_wait_cnt_tag {
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u32 reg;
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struct {
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u32 RTRY_WAIT_CNT:8;
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u32 :24;
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} fld;
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} RETRY_WAIT_CNT_R;
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typedef union int_csr_tag {
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u32 reg;
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struct {
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u32 FLD_END_EVE :1;
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u32 FLD_END_ODD :1;
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u32 FLD_START :1;
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u32 :5;
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u32 FLD_END_EVE_EN:1;
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u32 FLD_END_ODD_EN:1;
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u32 FLD_START_EN :1;
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u32 :21;
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} fld;
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} INT_CSR_R;
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typedef union mask_length_tag {
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u32 reg;
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struct {
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u32 MASK_LEN_EVE:5;
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u32 :11;
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u32 MASK_LEN_ODD:5;
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u32 :11;
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} fld;
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} MASK_LENGTH_R;
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typedef union fifo_flag_cnt_tag {
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u32 reg;
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struct {
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u32 AF_COUNT:7;
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u32 :9;
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u32 AE_COUNT:7;
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u32 :9;
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} fld;
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} FIFO_FLAG_CNT_R;
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typedef union iic_clk_dur {
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u32 reg;
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struct {
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u32 PHASE_1:8;
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u32 PHASE_2:8;
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u32 PHASE_3:8;
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u32 PHASE_4:8;
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} fld;
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} IIC_CLK_DUR_R;
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typedef union iic_csr1_tag {
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u32 reg;
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struct {
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u32 AUTO_EN :1;
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u32 BYPASS :1;
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u32 SDA_OUT :1;
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u32 SCL_OUT :1;
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u32 :4;
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u32 AUTO_ABORT :1;
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u32 DIRECT_ABORT:1;
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u32 SDA_IN :1;
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u32 SCL_IN :1;
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u32 :4;
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u32 AUTO_ADDR :8;
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u32 RD_DATA :8;
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} fld;
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} IIC_CSR1_R;
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/**********************************
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* iic_csr2_tag
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*/
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typedef union iic_csr2_tag {
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u32 reg;
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struct {
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u32 DIR_WR_DATA :8;
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u32 DIR_SUB_ADDR:8;
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u32 DIR_RD :1;
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u32 DIR_ADDR :7;
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u32 NEW_CYCLE :1;
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u32 :7;
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} fld;
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} IIC_CSR2_R;
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/* use for both EVEN and ODD DMA UPPER LIMITS */
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/*
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* dma_upper_lmt_tag
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*/
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typedef union dma_upper_lmt_tag {
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u32 reg;
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struct {
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u32 DMA_UPPER_LMT_VAL:24;
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u32 :8;
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} fld;
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} DMA_UPPER_LMT_R;
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/*
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* Global declarations of local copies of boards' 32 bit registers
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*/
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extern u32 even_dma_start_r; /* bit 0 should always be 0 */
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extern u32 odd_dma_start_r; /* .. */
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extern u32 even_dma_stride_r; /* bits 0&1 should always be 0 */
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extern u32 odd_dma_stride_r; /* .. */
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extern u32 even_pixel_fmt_r;
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extern u32 odd_pixel_fmt_r;
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extern FIFO_TRIGGER_R fifo_trigger_r;
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extern XFER_MODE_R xfer_mode_r;
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extern CSR1_R csr1_r;
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extern RETRY_WAIT_CNT_R retry_wait_cnt_r;
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extern INT_CSR_R int_csr_r;
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extern u32 even_fld_mask_r;
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extern u32 odd_fld_mask_r;
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extern MASK_LENGTH_R mask_length_r;
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extern FIFO_FLAG_CNT_R fifo_flag_cnt_r;
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extern IIC_CLK_DUR_R iic_clk_dur_r;
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extern IIC_CSR1_R iic_csr1_r;
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extern IIC_CSR2_R iic_csr2_r;
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extern DMA_UPPER_LMT_R even_dma_upper_lmt_r;
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extern DMA_UPPER_LMT_R odd_dma_upper_lmt_r;
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/***************** 8 bit I2C register globals ***********/
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#define CSR2 0x010 /* indices of 8-bit I2C mapped reg's*/
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#define EVEN_CSR 0x011
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#define ODD_CSR 0x012
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#define CONFIG 0x013
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#define DT_ID 0x01F
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#define X_CLIP_START 0x020
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#define Y_CLIP_START 0x022
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#define X_CLIP_END 0x024
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#define Y_CLIP_END 0x026
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#define AD_ADDR 0x030
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#define AD_LUT 0x031
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#define AD_CMD 0x032
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#define DIG_OUT 0x040
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#define PM_LUT_ADDR 0x050
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#define PM_LUT_DATA 0x051
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/******** Assignments and Typedefs for 8 bit I2C Registers********************/
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typedef union i2c_csr2_tag {
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u8 reg;
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struct {
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u8 CHROM_FIL:1;
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u8 SYNC_SNTL:1;
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u8 HZ50:1;
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u8 SYNC_PRESENT:1;
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u8 BUSY_EVE:1;
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u8 BUSY_ODD:1;
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u8 DISP_PASS:1;
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} fld;
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} I2C_CSR2;
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typedef union i2c_even_csr_tag {
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u8 reg;
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struct {
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u8 DONE_EVE :1;
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u8 SNGL_EVE :1;
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u8 ERROR_EVE:1;
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u8 :5;
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} fld;
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} I2C_EVEN_CSR;
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typedef union i2c_odd_csr_tag {
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u8 reg;
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struct {
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u8 DONE_ODD:1;
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u8 SNGL_ODD:1;
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u8 ERROR_ODD:1;
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u8 :5;
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} fld;
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} I2C_ODD_CSR;
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typedef union i2c_config_tag {
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u8 reg;
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struct {
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u8 ACQ_MODE:2;
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u8 EXT_TRIG_EN:1;
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u8 EXT_TRIG_POL:1;
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u8 H_SCALE:1;
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u8 CLIP:1;
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u8 PM_LUT_SEL:1;
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u8 PM_LUT_PGM:1;
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} fld;
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} I2C_CONFIG;
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typedef union i2c_ad_cmd_tag {
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/* bits can have 3 different meanings depending on value of AD_ADDR */
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u8 reg;
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/* Bt252 Command Register if AD_ADDR = 00h */
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struct {
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u8 :2;
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u8 SYNC_LVL_SEL:2;
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u8 SYNC_CNL_SEL:2;
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u8 DIGITIZE_CNL_SEL1:2;
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} bt252_command;
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/* Bt252 IOUT0 register if AD_ADDR = 01h */
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struct {
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u8 IOUT_DATA:8;
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} bt252_iout0;
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/* BT252 IOUT1 register if AD_ADDR = 02h */
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struct {
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u8 IOUT_DATA:8;
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} bt252_iout1;
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} I2C_AD_CMD;
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/***** Global declarations of local copies of boards' 8 bit I2C registers ***/
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extern I2C_CSR2 i2c_csr2;
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extern I2C_EVEN_CSR i2c_even_csr;
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extern I2C_ODD_CSR i2c_odd_csr;
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extern I2C_CONFIG i2c_config;
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extern u8 i2c_dt_id;
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extern u8 i2c_x_clip_start;
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extern u8 i2c_y_clip_start;
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extern u8 i2c_x_clip_end;
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extern u8 i2c_y_clip_end;
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extern u8 i2c_ad_addr;
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extern u8 i2c_ad_lut;
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extern I2C_AD_CMD i2c_ad_cmd;
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extern u8 i2c_dig_out;
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extern u8 i2c_pm_lut_addr;
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extern u8 i2c_pm_lut_data;
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/* Functions for Global use */
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/* access 8-bit IIC registers */
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extern int ReadI2C(u8 *lpReg, u_short wIregIndex, u8 *byVal);
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extern int WriteI2C(u8 *lpReg, u_short wIregIndex, u8 byVal);
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#endif
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