4d5f9cdacb
Several of the macros in mx31ads.h depend on mx31.h which is no longer included in quite so many standard headers as it once was. Include it directly so we can build. Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
123 lines
3.8 KiB
C
123 lines
3.8 KiB
C
/*
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* Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_ARCH_MXC_BOARD_MX31ADS_H__
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#define __ASM_ARCH_MXC_BOARD_MX31ADS_H__
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#include <mach/hardware.h>
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/* Base address of PBC controller */
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#define PBC_BASE_ADDRESS IO_ADDRESS(CS4_BASE_ADDR)
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/* Offsets for the PBC Controller register */
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/* PBC Board status register offset */
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#define PBC_BSTAT 0x000002
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/* PBC Board control register 1 set address */
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#define PBC_BCTRL1_SET 0x000004
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/* PBC Board control register 1 clear address */
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#define PBC_BCTRL1_CLEAR 0x000006
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/* PBC Board control register 2 set address */
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#define PBC_BCTRL2_SET 0x000008
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/* PBC Board control register 2 clear address */
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#define PBC_BCTRL2_CLEAR 0x00000A
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/* PBC Board control register 3 set address */
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#define PBC_BCTRL3_SET 0x00000C
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/* PBC Board control register 3 clear address */
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#define PBC_BCTRL3_CLEAR 0x00000E
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/* PBC Board control register 4 set address */
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#define PBC_BCTRL4_SET 0x000010
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/* PBC Board control register 4 clear address */
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#define PBC_BCTRL4_CLEAR 0x000012
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/* PBC Board status register 1 */
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#define PBC_BSTAT1 0x000014
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/* PBC Board interrupt status register */
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#define PBC_INTSTATUS 0x000016
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/* PBC Board interrupt current status register */
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#define PBC_INTCURR_STATUS 0x000018
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/* PBC Interrupt mask register set address */
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#define PBC_INTMASK_SET 0x00001A
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/* PBC Interrupt mask register clear address */
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#define PBC_INTMASK_CLEAR 0x00001C
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/* External UART A */
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#define PBC_SC16C652_UARTA 0x010000
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/* External UART B */
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#define PBC_SC16C652_UARTB 0x010010
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/* Ethernet Controller IO base address */
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#define PBC_CS8900A_IOBASE 0x020000
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/* Ethernet Controller Memory base address */
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#define PBC_CS8900A_MEMBASE 0x021000
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/* Ethernet Controller DMA base address */
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#define PBC_CS8900A_DMABASE 0x022000
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/* External chip select 0 */
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#define PBC_XCS0 0x040000
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/* LCD Display enable */
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#define PBC_LCD_EN_B 0x060000
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/* Code test debug enable */
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#define PBC_CODE_B 0x070000
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/* PSRAM memory select */
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#define PBC_PSRAM_B 0x5000000
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#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
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#define PBC_INTCURR_STATUS_REG (PBC_INTCURR_STATUS + PBC_BASE_ADDRESS)
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#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
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#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
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#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
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#define MXC_EXP_IO_BASE (MXC_BOARD_IRQ_START)
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#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
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#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 0)
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#define EXPIO_INT_PB_IRQ (MXC_EXP_IO_BASE + 1)
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#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
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#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
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#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
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#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
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#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
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#define EXPIO_INT_RES7 (MXC_EXP_IO_BASE + 7)
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#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
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#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
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#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
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#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
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#define EXPIO_INT_SYNTH_IRQ (MXC_EXP_IO_BASE + 12)
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#define EXPIO_INT_CE_INT1 (MXC_EXP_IO_BASE + 13)
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#define EXPIO_INT_CE_INT2 (MXC_EXP_IO_BASE + 14)
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#define EXPIO_INT_RES15 (MXC_EXP_IO_BASE + 15)
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#define MXC_MAX_EXP_IO_LINES 16
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/* mandatory for CONFIG_LL_DEBUG */
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#define MXC_LL_UART_PADDR UART1_BASE_ADDR
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#define MXC_LL_UART_VADDR AIPS1_IO_ADDRESS(UART1_BASE_ADDR)
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#endif /* __ASM_ARCH_MXC_BOARD_MX31ADS_H__ */
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