39b8d52542
Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
70 lines
1.5 KiB
C
70 lines
1.5 KiB
C
#ifndef _ASM_SMTC_MT_H
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#define _ASM_SMTC_MT_H
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/*
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* Definitions for SMTC multitasking on MIPS MT cores
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*/
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#include <asm/mips_mt.h>
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/*
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* System-wide SMTC status information
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*/
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extern unsigned int smtc_status;
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#define SMTC_TLB_SHARED 0x00000001
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#define SMTC_MTC_ACTIVE 0x00000002
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/*
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* TLB/ASID Management information
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*/
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#define MAX_SMTC_TLBS 2
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#define MAX_SMTC_ASIDS 256
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#if NR_CPUS <= 8
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typedef char asiduse;
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#else
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#if NR_CPUS <= 16
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typedef short asiduse;
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#else
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typedef long asiduse;
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#endif
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#endif
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extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
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struct mm_struct;
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struct task_struct;
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void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
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void smtc_flush_tlb_asid(unsigned long asid);
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extern int mipsmt_build_cpu_map(int startslot);
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extern void mipsmt_prepare_cpus(void);
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extern void smtc_smp_finish(void);
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extern void smtc_boot_secondary(int cpu, struct task_struct *t);
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extern void smtc_cpus_done(void);
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/*
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* Sharing the TLB between multiple VPEs means that the
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* "random" index selection function is not allowed to
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* select the current value of the Index register. To
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* avoid additional TLB pressure, the Index registers
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* are "parked" with an non-Valid value.
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*/
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#define PARKED_INDEX ((unsigned int)0x80000000)
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/*
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* Define low-level interrupt mask for IPIs, if necessary.
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* By default, use SW interrupt 1, which requires no external
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* hardware support, but which works only for single-core
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* MIPS MT systems.
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*/
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#ifndef MIPS_CPU_IPI_IRQ
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#define MIPS_CPU_IPI_IRQ 1
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#endif
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#endif /* _ASM_SMTC_MT_H */
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