92b9679711
Add pristine upstream vt6656 driver sources to drivers/staging/vt6656. These files were copied from the driver directory in the upstream source archive, available here: http://www.viaarena.com/Driver/VT6656_Linux_src_v1.19_12_x86.zip After copying, trailing whitespace was stripped. This is GPL-licensed code. Signed-off-by: Forest Bond <forest@alittletooquiet.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
459 lines
14 KiB
C
459 lines
14 KiB
C
/*
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* Copyright (c) 1996, 2003 VIA Networking Technologies, Inc.
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* All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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*
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* File: mac.h
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*
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* Purpose: MAC routines
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*
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* Author: Tevin Chen
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*
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* Date: May 21, 1996
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*
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* Revision History:
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* 07-01-2003 Bryan YC Fan: Re-write codes to support VT3253 spec.
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* 08-25-2003 Kyle Hsu: Porting MAC functions from sim53.
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* 09-03-2003 Bryan YC Fan: Add MACvDisableProtectMD & MACvEnableProtectMD
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*/
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#ifndef __MAC_H__
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#define __MAC_H__
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#if !defined(__TTYPE_H__)
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#include "ttype.h"
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#endif
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#if !defined(__DEVICE_H__)
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#include "device.h"
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#endif
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#if !defined(__TMACRO_H__)
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#include "tmacro.h"
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#endif
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#if !defined(__UMEM_H__)
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#include "umem.h"
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#endif
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/*--------------------- Export Definitions -------------------------*/
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#define REV_ID_VT3253_A0 0x00
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#define REV_ID_VT3253_A1 0x01
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#define REV_ID_VT3253_B0 0x08
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#define REV_ID_VT3253_B1 0x09
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//
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// Registers in the MAC
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//
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#define MAC_REG_BISTCMD 0x04
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#define MAC_REG_BISTSR0 0x05
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#define MAC_REG_BISTSR1 0x06
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#define MAC_REG_BISTSR2 0x07
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#define MAC_REG_I2MCSR 0x08
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#define MAC_REG_I2MTGID 0x09
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#define MAC_REG_I2MTGAD 0x0A
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#define MAC_REG_I2MCFG 0x0B
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#define MAC_REG_I2MDIPT 0x0C
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#define MAC_REG_I2MDOPT 0x0E
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#define MAC_REG_USBSUS 0x0F
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#define MAC_REG_LOCALID 0x14
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#define MAC_REG_TESTCFG 0x15
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#define MAC_REG_JUMPER0 0x16
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#define MAC_REG_JUMPER1 0x17
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#define MAC_REG_TMCTL 0x18
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#define MAC_REG_TMDATA0 0x1C
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#define MAC_REG_TMDATA1 0x1D
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#define MAC_REG_TMDATA2 0x1E
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#define MAC_REG_TMDATA3 0x1F
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// MAC Parameter related
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#define MAC_REG_LRT 0x20 //
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#define MAC_REG_SRT 0x21 //
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#define MAC_REG_SIFS 0x22 //
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#define MAC_REG_DIFS 0x23 //
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#define MAC_REG_EIFS 0x24 //
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#define MAC_REG_SLOT 0x25 //
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#define MAC_REG_BI 0x26 //
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#define MAC_REG_CWMAXMIN0 0x28 //
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#define MAC_REG_LINKOFFTOTM 0x2A
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#define MAC_REG_SWTMOT 0x2B
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#define MAC_REG_RTSOKCNT 0x2C
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#define MAC_REG_RTSFAILCNT 0x2D
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#define MAC_REG_ACKFAILCNT 0x2E
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#define MAC_REG_FCSERRCNT 0x2F
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// TSF Related
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#define MAC_REG_TSFCNTR 0x30 //
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#define MAC_REG_NEXTTBTT 0x38 //
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#define MAC_REG_TSFOFST 0x40 //
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#define MAC_REG_TFTCTL 0x48 //
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// WMAC Control/Status Related
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#define MAC_REG_ENCFG0 0x4C //
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#define MAC_REG_ENCFG1 0x4D //
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#define MAC_REG_ENCFG2 0x4E //
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#define MAC_REG_CFG 0x50 //
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#define MAC_REG_TEST 0x52 //
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#define MAC_REG_HOSTCR 0x54 //
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#define MAC_REG_MACCR 0x55 //
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#define MAC_REG_RCR 0x56 //
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#define MAC_REG_TCR 0x57 //
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#define MAC_REG_IMR 0x58 //
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#define MAC_REG_ISR 0x5C
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#define MAC_REG_ISR1 0x5D
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// Power Saving Related
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#define MAC_REG_PSCFG 0x60 //
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#define MAC_REG_PSCTL 0x61 //
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#define MAC_REG_PSPWRSIG 0x62 //
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#define MAC_REG_BBCR13 0x63
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#define MAC_REG_AIDATIM 0x64
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#define MAC_REG_PWBT 0x66
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#define MAC_REG_WAKEOKTMR 0x68
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#define MAC_REG_CALTMR 0x69
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#define MAC_REG_SYNSPACCNT 0x6A
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#define MAC_REG_WAKSYNOPT 0x6B
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// Baseband/IF Control Group
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#define MAC_REG_BBREGCTL 0x6C //
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#define MAC_REG_CHANNEL 0x6D
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#define MAC_REG_BBREGADR 0x6E
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#define MAC_REG_BBREGDATA 0x6F
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#define MAC_REG_IFREGCTL 0x70 //
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#define MAC_REG_IFDATA 0x71 //
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#define MAC_REG_ITRTMSET 0x74 //
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#define MAC_REG_PAPEDELAY 0x77
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#define MAC_REG_SOFTPWRCTL 0x78 //
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#define MAC_REG_SOFTPWRCTL2 0x79 //
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#define MAC_REG_GPIOCTL0 0x7A //
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#define MAC_REG_GPIOCTL1 0x7B //
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// MiscFF PIO related
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#define MAC_REG_MISCFFNDEX 0xBC
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#define MAC_REG_MISCFFCTL 0xBE
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#define MAC_REG_MISCFFDATA 0xC0
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// MAC Configuration Group
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#define MAC_REG_PAR0 0xC4
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#define MAC_REG_PAR4 0xC8
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#define MAC_REG_BSSID0 0xCC
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#define MAC_REG_BSSID4 0xD0
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#define MAC_REG_MAR0 0xD4
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#define MAC_REG_MAR4 0xD8
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// MAC RSPPKT INFO Group
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#define MAC_REG_RSPINF_B_1 0xDC
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#define MAC_REG_RSPINF_B_2 0xE0
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#define MAC_REG_RSPINF_B_5 0xE4
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#define MAC_REG_RSPINF_B_11 0xE8
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#define MAC_REG_RSPINF_A_6 0xEC
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#define MAC_REG_RSPINF_A_9 0xEE
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#define MAC_REG_RSPINF_A_12 0xF0
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#define MAC_REG_RSPINF_A_18 0xF2
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#define MAC_REG_RSPINF_A_24 0xF4
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#define MAC_REG_RSPINF_A_36 0xF6
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#define MAC_REG_RSPINF_A_48 0xF8
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#define MAC_REG_RSPINF_A_54 0xFA
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#define MAC_REG_RSPINF_A_72 0xFC
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//
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// Bits in the I2MCFG EEPROM register
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//
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#define I2MCFG_BOUNDCTL 0x80
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#define I2MCFG_WAITCTL 0x20
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#define I2MCFG_SCLOECTL 0x10
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#define I2MCFG_WBUSYCTL 0x08
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#define I2MCFG_NORETRY 0x04
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#define I2MCFG_I2MLDSEQ 0x02
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#define I2MCFG_I2CMFAST 0x01
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//
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// Bits in the I2MCSR EEPROM register
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//
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#define I2MCSR_EEMW 0x80
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#define I2MCSR_EEMR 0x40
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#define I2MCSR_AUTOLD 0x08
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#define I2MCSR_NACK 0x02
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#define I2MCSR_DONE 0x01
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//
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// Bits in the TMCTL register
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//
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#define TMCTL_TSUSP 0x04
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#define TMCTL_TMD 0x02
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#define TMCTL_TE 0x01
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//
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// Bits in the TFTCTL register
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//
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#define TFTCTL_HWUTSF 0x80 //
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#define TFTCTL_TBTTSYNC 0x40
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#define TFTCTL_HWUTSFEN 0x20
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#define TFTCTL_TSFCNTRRD 0x10 //
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#define TFTCTL_TBTTSYNCEN 0x08 //
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#define TFTCTL_TSFSYNCEN 0x04 //
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#define TFTCTL_TSFCNTRST 0x02 //
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#define TFTCTL_TSFCNTREN 0x01 //
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//
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// Bits in the EnhanceCFG_0 register
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//
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#define EnCFG_BBType_a 0x00
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#define EnCFG_BBType_b 0x01
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#define EnCFG_BBType_g 0x02
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#define EnCFG_BBType_MASK 0x03
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#define EnCFG_ProtectMd 0x20
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//
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// Bits in the EnhanceCFG_1 register
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//
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#define EnCFG_BcnSusInd 0x01
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#define EnCFG_BcnSusClr 0x02
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//
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// Bits in the EnhanceCFG_2 register
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//
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#define EnCFG_NXTBTTCFPSTR 0x01
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#define EnCFG_BarkerPream 0x02
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#define EnCFG_PktBurstMode 0x04
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//
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// Bits in the CFG register
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//
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#define CFG_TKIPOPT 0x80
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#define CFG_RXDMAOPT 0x40
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#define CFG_TMOT_SW 0x20
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#define CFG_TMOT_HWLONG 0x10
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#define CFG_TMOT_HW 0x00
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#define CFG_CFPENDOPT 0x08
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#define CFG_BCNSUSEN 0x04
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#define CFG_NOTXTIMEOUT 0x02
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#define CFG_NOBUFOPT 0x01
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//
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// Bits in the TEST register
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//
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#define TEST_LBEXT 0x80 //
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#define TEST_LBINT 0x40 //
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#define TEST_LBNONE 0x00 //
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#define TEST_SOFTINT 0x20 //
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#define TEST_CONTTX 0x10 //
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#define TEST_TXPE 0x08 //
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#define TEST_NAVDIS 0x04 //
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#define TEST_NOCTS 0x02 //
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#define TEST_NOACK 0x01 //
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//
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// Bits in the HOSTCR register
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//
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#define HOSTCR_TXONST 0x80 //
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#define HOSTCR_RXONST 0x40 //
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#define HOSTCR_ADHOC 0x20 // Network Type 1 = Ad-hoc
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#define HOSTCR_AP 0x10 // Port Type 1 = AP
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#define HOSTCR_TXON 0x08 //0000 1000
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#define HOSTCR_RXON 0x04 //0000 0100
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#define HOSTCR_MACEN 0x02 //0000 0010
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#define HOSTCR_SOFTRST 0x01 //0000 0001
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//
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// Bits in the MACCR register
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//
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#define MACCR_SYNCFLUSHOK 0x04 //
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#define MACCR_SYNCFLUSH 0x02 //
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#define MACCR_CLRNAV 0x01 //
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//
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// Bits in the RCR register
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//
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#define RCR_SSID 0x80
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#define RCR_RXALLTYPE 0x40 //
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#define RCR_UNICAST 0x20 //
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#define RCR_BROADCAST 0x10 //
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#define RCR_MULTICAST 0x08 //
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#define RCR_WPAERR 0x04 //
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#define RCR_ERRCRC 0x02 //
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#define RCR_BSSID 0x01 //
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//
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// Bits in the TCR register
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//
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#define TCR_SYNCDCFOPT 0x02 //
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#define TCR_AUTOBCNTX 0x01 // Beacon automatically transmit enable
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//ISR1
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#define ISR_GPIO3 0x40
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#define ISR_RXNOBUF 0x08
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#define ISR_MIBNEARFULL 0x04
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#define ISR_SOFTINT 0x02
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#define ISR_FETALERR 0x01
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#define LEDSTS_STS 0x06
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#define LEDSTS_TMLEN 0x78
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#define LEDSTS_OFF 0x00
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#define LEDSTS_ON 0x02
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#define LEDSTS_SLOW 0x04
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#define LEDSTS_INTER 0x06
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//ISR0
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#define ISR_WATCHDOG 0x80
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#define ISR_SOFTTIMER 0x40
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#define ISR_GPIO0 0x20
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#define ISR_TBTT 0x10
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#define ISR_RXDMA0 0x08
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#define ISR_BNTX 0x04
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#define ISR_ACTX 0x01
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//
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// Bits in the PSCFG register
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//
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#define PSCFG_PHILIPMD 0x40 //
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#define PSCFG_WAKECALEN 0x20 //
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#define PSCFG_WAKETMREN 0x10 //
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#define PSCFG_BBPSPROG 0x08 //
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#define PSCFG_WAKESYN 0x04 //
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#define PSCFG_SLEEPSYN 0x02 //
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#define PSCFG_AUTOSLEEP 0x01 //
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//
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// Bits in the PSCTL register
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//
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#define PSCTL_WAKEDONE 0x20 //
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#define PSCTL_PS 0x10 //
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#define PSCTL_GO2DOZE 0x08 //
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#define PSCTL_LNBCN 0x04 //
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#define PSCTL_ALBCN 0x02 //
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#define PSCTL_PSEN 0x01 //
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//
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// Bits in the PSPWSIG register
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//
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#define PSSIG_WPE3 0x80 //
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#define PSSIG_WPE2 0x40 //
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#define PSSIG_WPE1 0x20 //
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#define PSSIG_WRADIOPE 0x10 //
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#define PSSIG_SPE3 0x08 //
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#define PSSIG_SPE2 0x04 //
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#define PSSIG_SPE1 0x02 //
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#define PSSIG_SRADIOPE 0x01 //
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//
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// Bits in the BBREGCTL register
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//
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#define BBREGCTL_DONE 0x04 //
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#define BBREGCTL_REGR 0x02 //
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#define BBREGCTL_REGW 0x01 //
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//
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// Bits in the IFREGCTL register
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//
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#define IFREGCTL_DONE 0x04 //
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#define IFREGCTL_IFRF 0x02 //
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#define IFREGCTL_REGW 0x01 //
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//
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// Bits in the SOFTPWRCTL register
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//
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#define SOFTPWRCTL_RFLEOPT 0x08 //
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#define SOFTPWRCTL_TXPEINV 0x02 //
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#define SOFTPWRCTL_SWPECTI 0x01 //
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#define SOFTPWRCTL_SWPAPE 0x20 //
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#define SOFTPWRCTL_SWCALEN 0x10 //
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#define SOFTPWRCTL_SWRADIO_PE 0x08 //
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#define SOFTPWRCTL_SWPE2 0x04 //
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#define SOFTPWRCTL_SWPE1 0x02 //
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#define SOFTPWRCTL_SWPE3 0x01 //
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//
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// Bits in the GPIOCTL1 register
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//
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#define GPIO3_MD 0x20 //
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#define GPIO3_DATA 0x40 //
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#define GPIO3_INTMD 0x80 //
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//
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// Bits in the MISCFFCTL register
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//
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#define MISCFFCTL_WRITE 0x0001 //
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// Loopback mode
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#define MAC_LB_EXT 0x02 //
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#define MAC_LB_INTERNAL 0x01 //
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#define MAC_LB_NONE 0x00 //
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// Ethernet address filter type
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#define PKT_TYPE_NONE 0x00 // turn off receiver
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#define PKT_TYPE_ALL_MULTICAST 0x80
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#define PKT_TYPE_PROMISCUOUS 0x40
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#define PKT_TYPE_DIRECTED 0x20 // obselete, directed address is always accepted
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#define PKT_TYPE_BROADCAST 0x10
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#define PKT_TYPE_MULTICAST 0x08
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#define PKT_TYPE_ERROR_WPA 0x04
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#define PKT_TYPE_ERROR_CRC 0x02
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#define PKT_TYPE_BSSID 0x01
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#define Default_BI 0x200
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// MiscFIFO Offset
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#define MISCFIFO_KEYETRY0 32
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#define MISCFIFO_KEYENTRYSIZE 22
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// max time out delay time
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#define W_MAX_TIMEOUT 0xFFF0U //
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// wait time within loop
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#define CB_DELAY_LOOP_WAIT 10 // 10ms
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#define MAC_REVISION_A0 0x00
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#define MAC_REVISION_A1 0x01
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/*--------------------- Export Types ------------------------------*/
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/*--------------------- Export Macros ------------------------------*/
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/*--------------------- Export Classes ----------------------------*/
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/*--------------------- Export Variables --------------------------*/
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/*--------------------- Export Functions --------------------------*/
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#ifdef __cplusplus
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extern "C" { /* Assume C declarations for C++ */
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#endif /* __cplusplus */
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void MACvSetMultiAddrByHash (PSDevice pDevice, BYTE byHashIdx);
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VOID MACvWriteMultiAddr (PSDevice pDevice, UINT uByteIdx, BYTE byData);
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BOOL MACbShutdown(PSDevice pDevice);;
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void MACvSetBBType(PSDevice pDevice,BYTE byType);
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void MACvSetMISCFifo (PSDevice pDevice, WORD wOffset, DWORD dwData);
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void MACvDisableKeyEntry(PSDevice pDevice, UINT uEntryIdx);
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void MACvSetKeyEntry(PSDevice pDevice, WORD wKeyCtl, UINT uEntryIdx, UINT uKeyIdx, PBYTE pbyAddr, PDWORD pdwKey);
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void MACvRegBitsOff(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
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void MACvRegBitsOn(PSDevice pDevice, BYTE byRegOfs, BYTE byBits);
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void MACvWriteWord(PSDevice pDevice, BYTE byRegOfs, WORD wData);
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void MACvWriteBSSIDAddress(PSDevice pDevice, PBYTE pbyEtherAddr);
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void MACvEnableProtectMD(PSDevice pDevice);
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void MACvDisableProtectMD(PSDevice pDevice);
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void MACvEnableBarkerPreambleMd(PSDevice pDevice);
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void MACvDisableBarkerPreambleMd(PSDevice pDevice);
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void MACvWriteBeaconInterval(PSDevice pDevice, WORD wInterval);
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#ifdef __cplusplus
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} /* End of extern "C" { */
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#endif /* __cplusplus */
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#endif // __MAC_H__
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