84542838a3
INKERNEL is always defined HOST is never defined therefore RTA is also never defined Strip the relevant garbage out of the headers on this basis. Signed-off-by: Alan Cox <alan@redhat.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
322 lines
12 KiB
C
322 lines
12 KiB
C
/****************************************************************************
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******* *******
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******* CIRRUS.H *******
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******* *******
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****************************************************************************
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Author : Jeremy Rolls
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Date : 3 Aug 1990
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*
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* (C) 1990 - 2000 Specialix International Ltd., Byfleet, Surrey, UK.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Version : 0.01
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Mods
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----------------------------------------------------------------------------
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Date By Description
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----------------------------------------------------------------------------
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***************************************************************************/
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#ifndef _cirrus_h
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#ifndef lint
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/* static char* _cirrus_h_sccs = "@(#)cirrus.h 1.16"; */
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#endif
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#define _cirrus_h 1
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/* Bit fields for particular registers */
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/* GCR */
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#define GCR_SERIAL 0x00 /* Configure as serial channel */
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#define GCR_PARALLEL 0x80 /* Configure as parallel channel */
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/* RDSR - when status read from FIFO */
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#define RDSR_BREAK 0x08 /* Break received */
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#define RDSR_TIMEOUT 0x80 /* No new data timeout */
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#define RDSR_SC1 0x10 /* Special char 1 (tx XON) matched */
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#define RDSR_SC2 0x20 /* Special char 2 (tx XOFF) matched */
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#define RDSR_SC12_MASK 0x30 /* Mask for special chars 1 and 2 */
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/* PPR */
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#define PPR_DEFAULT 0x31 /* Default value - for a 25Mhz clock gives
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a timeout period of 1ms */
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/* LIVR */
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#define LIVR_EXCEPTION 0x07 /* Receive exception interrupt */
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/* CCR */
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#define CCR_RESET 0x80 /* Reset channel */
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#define CCR_CHANGE 0x4e /* COR's have changed - NB always change all
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COR's */
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#define CCR_WFLUSH 0x82 /* Flush transmit FIFO and TSR / THR */
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#define CCR_SENDSC1 0x21 /* Send special character one */
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#define CCR_SENDSC2 0x22 /* Send special character two */
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#define CCR_SENDSC3 0x23 /* Send special character three */
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#define CCR_SENDSC4 0x24 /* Send special character four */
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#define CCR_TENABLE 0x18 /* Enable transmitter */
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#define CCR_TDISABLE 0x14 /* Disable transmitter */
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#define CCR_RENABLE 0x12 /* Enable receiver */
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#define CCR_RDISABLE 0x11 /* Disable receiver */
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#define CCR_READY 0x00 /* CCR is ready for another command */
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/* CCSR */
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#define CCSR_TXENABLE 0x08 /* Transmitter enable */
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#define CCSR_RXENABLE 0x80 /* Receiver enable */
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#define CCSR_TXFLOWOFF 0x04 /* Transmit flow off */
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#define CCSR_TXFLOWON 0x02 /* Transmit flow on */
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/* SVRR */
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#define SVRR_RECEIVE 0x01 /* Receive interrupt pending */
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#define SVRR_TRANSMIT 0x02 /* Transmit interrupt pending */
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#define SVRR_MODEM 0x04 /* Modem interrupt pending */
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/* CAR */
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#define CAR_PORTS 0x03 /* Bit fields for ports */
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/* IER */
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#define IER_MODEM 0x80 /* Change in modem status */
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#define IER_RECEIVE 0x10 /* Good data / data exception */
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#define IER_TRANSMITR 0x04 /* Transmit ready (FIFO empty) */
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#define IER_TRANSMITE 0x02 /* Transmit empty */
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#define IER_TIMEOUT 0x01 /* Timeout on no data */
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#define IER_DEFAULT 0x94 /* Default values */
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#define IER_PARALLEL 0x84 /* Default for Parallel */
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#define IER_EMPTY 0x92 /* Transmitter empty rather than ready */
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/* COR1 - Driver only */
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#define COR1_INPCK 0x10 /* Check parity of received characters */
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/* COR1 - driver and RTA */
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#define COR1_ODD 0x80 /* Odd parity */
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#define COR1_EVEN 0x00 /* Even parity */
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#define COR1_NOP 0x00 /* No parity */
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#define COR1_FORCE 0x20 /* Force parity */
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#define COR1_NORMAL 0x40 /* With parity */
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#define COR1_1STOP 0x00 /* 1 stop bit */
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#define COR1_15STOP 0x04 /* 1.5 stop bits */
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#define COR1_2STOP 0x08 /* 2 stop bits */
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#define COR1_5BITS 0x00 /* 5 data bits */
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#define COR1_6BITS 0x01 /* 6 data bits */
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#define COR1_7BITS 0x02 /* 7 data bits */
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#define COR1_8BITS 0x03 /* 8 data bits */
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#define COR1_HOST 0xef /* Safe host bits */
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/* RTA only */
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#define COR1_CINPCK 0x00 /* Check parity of received characters */
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#define COR1_CNINPCK 0x10 /* Don't check parity */
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/* COR2 bits for both RTA and driver use */
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#define COR2_IXANY 0x80 /* IXANY - any character is XON */
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#define COR2_IXON 0x40 /* IXON - enable tx soft flowcontrol */
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#define COR2_RTSFLOW 0x02 /* Enable tx hardware flow control */
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/* Additional driver bits */
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#define COR2_HUPCL 0x20 /* Hang up on close */
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#define COR2_CTSFLOW 0x04 /* Enable rx hardware flow control */
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#define COR2_IXOFF 0x01 /* Enable rx software flow control */
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#define COR2_DTRFLOW 0x08 /* Enable tx hardware flow control */
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/* RTA use only */
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#define COR2_ETC 0x20 /* Embedded transmit options */
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#define COR2_LOCAL 0x10 /* Local loopback mode */
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#define COR2_REMOTE 0x08 /* Remote loopback mode */
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#define COR2_HOST 0xc2 /* Safe host bits */
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/* COR3 - RTA use only */
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#define COR3_SCDRNG 0x80 /* Enable special char detect for range */
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#define COR3_SCD34 0x40 /* Special character detect for SCHR's 3 + 4 */
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#define COR3_FCT 0x20 /* Flow control transparency */
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#define COR3_SCD12 0x10 /* Special character detect for SCHR's 1 + 2 */
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#define COR3_FIFO12 0x0c /* 12 chars for receive FIFO threshold */
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#define COR3_FIFO10 0x0a /* 10 chars for receive FIFO threshold */
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#define COR3_FIFO8 0x08 /* 8 chars for receive FIFO threshold */
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#define COR3_FIFO6 0x06 /* 6 chars for receive FIFO threshold */
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#define COR3_THRESHOLD COR3_FIFO8 /* MUST BE LESS THAN MCOR_THRESHOLD */
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#define COR3_DEFAULT (COR3_FCT | COR3_THRESHOLD)
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/* Default bits for COR3 */
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/* COR4 driver and RTA use */
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#define COR4_IGNCR 0x80 /* Throw away CR's on input */
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#define COR4_ICRNL 0x40 /* Map CR -> NL on input */
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#define COR4_INLCR 0x20 /* Map NL -> CR on input */
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#define COR4_IGNBRK 0x10 /* Ignore Break */
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#define COR4_NBRKINT 0x08 /* No interrupt on break (-BRKINT) */
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#define COR4_RAISEMOD 0x01 /* Raise modem output lines on non-zero baud */
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/* COR4 driver only */
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#define COR4_IGNPAR 0x04 /* IGNPAR (ignore characters with errors) */
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#define COR4_PARMRK 0x02 /* PARMRK */
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#define COR4_HOST 0xf8 /* Safe host bits */
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/* COR4 RTA only */
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#define COR4_CIGNPAR 0x02 /* Thrown away bad characters */
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#define COR4_CPARMRK 0x04 /* PARMRK characters */
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#define COR4_CNPARMRK 0x03 /* Don't PARMRK */
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/* COR5 driver and RTA use */
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#define COR5_ISTRIP 0x80 /* Strip input chars to 7 bits */
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#define COR5_LNE 0x40 /* Enable LNEXT processing */
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#define COR5_CMOE 0x20 /* Match good and errored characters */
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#define COR5_ONLCR 0x02 /* NL -> CR NL on output */
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#define COR5_OCRNL 0x01 /* CR -> NL on output */
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/*
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** Spare bits - these are not used in the CIRRUS registers, so we use
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** them to set various other features.
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*/
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/*
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** tstop and tbusy indication
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*/
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#define COR5_TSTATE_ON 0x08 /* Turn on monitoring of tbusy and tstop */
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#define COR5_TSTATE_OFF 0x04 /* Turn off monitoring of tbusy and tstop */
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/*
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** TAB3
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*/
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#define COR5_TAB3 0x10 /* TAB3 mode */
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#define COR5_HOST 0xc3 /* Safe host bits */
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/* CCSR */
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#define CCSR_TXFLOFF 0x04 /* Tx is xoffed */
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/* MSVR1 */
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/* NB. DTR / CD swapped from Cirrus spec as the pins are also reversed on the
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RTA. This is because otherwise DCD would get lost on the 1 parallel / 3
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serial option.
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*/
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#define MSVR1_CD 0x80 /* CD (DSR on Cirrus) */
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#define MSVR1_RTS 0x40 /* RTS (CTS on Cirrus) */
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#define MSVR1_RI 0x20 /* RI */
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#define MSVR1_DTR 0x10 /* DTR (CD on Cirrus) */
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#define MSVR1_CTS 0x01 /* CTS output pin (RTS on Cirrus) */
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/* Next two used to indicate state of tbusy and tstop to driver */
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#define MSVR1_TSTOP 0x08 /* Set if port flow controlled */
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#define MSVR1_TEMPTY 0x04 /* Set if port tx buffer empty */
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#define MSVR1_HOST 0xf3 /* The bits the host wants */
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/* MSVR2 */
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#define MSVR2_DSR 0x02 /* DSR output pin (DTR on Cirrus) */
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/* MCOR */
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#define MCOR_CD 0x80 /* CD (DSR on Cirrus) */
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#define MCOR_RTS 0x40 /* RTS (CTS on Cirrus) */
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#define MCOR_RI 0x20 /* RI */
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#define MCOR_DTR 0x10 /* DTR (CD on Cirrus) */
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#define MCOR_DEFAULT (MCOR_CD | MCOR_RTS | MCOR_RI | MCOR_DTR)
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#define MCOR_FULLMODEM MCOR_DEFAULT
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#define MCOR_RJ45 (MCOR_CD | MCOR_RTS | MCOR_DTR)
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#define MCOR_RESTRICTED (MCOR_CD | MCOR_RTS)
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/* More MCOR - H/W Handshake (flowcontrol) stuff */
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#define MCOR_THRESH8 0x08 /* eight characters then we stop */
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#define MCOR_THRESH9 0x09 /* nine characters then we stop */
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#define MCOR_THRESH10 0x0A /* ten characters then we stop */
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#define MCOR_THRESH11 0x0B /* eleven characters then we stop */
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#define MCOR_THRESHBITS 0x0F /* mask for ANDing out the above */
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#define MCOR_THRESHOLD MCOR_THRESH9 /* MUST BE GREATER THAN COR3_THRESHOLD */
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/* RTPR */
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#define RTPR_DEFAULT 0x02 /* Default */
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/* Defines for the subscripts of a CONFIG packet */
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#define CONFIG_COR1 1 /* Option register 1 */
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#define CONFIG_COR2 2 /* Option register 2 */
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#define CONFIG_COR4 3 /* Option register 4 */
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#define CONFIG_COR5 4 /* Option register 5 */
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#define CONFIG_TXXON 5 /* Tx XON character */
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#define CONFIG_TXXOFF 6 /* Tx XOFF character */
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#define CONFIG_RXXON 7 /* Rx XON character */
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#define CONFIG_RXXOFF 8 /* Rx XOFF character */
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#define CONFIG_LNEXT 9 /* LNEXT character */
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#define CONFIG_TXBAUD 10 /* Tx baud rate */
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#define CONFIG_RXBAUD 11 /* Rx baud rate */
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/* Port status stuff */
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#define IDLE_CLOSED 0 /* Closed */
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#define IDLE_OPEN 1 /* Idle open */
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#define IDLE_BREAK 2 /* Idle on break */
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/* Subscript of MODEM STATUS packet */
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#define MODEM_VALUE 3 /* Current values of handshake pins */
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/* Subscript of SBREAK packet */
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#define BREAK_LENGTH 1 /* Length of a break in slices of 0.01 seconds
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0 = stay on break until an EBREAK command
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is sent */
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#define PRE_EMPTIVE 0x80 /* Pre-emptive bit in command field */
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/* Packet types going from Host to remote - with the exception of OPEN, MOPEN,
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CONFIG, SBREAK and MEMDUMP the remaining bytes of the data array will not
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be used
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*/
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#define OPEN 0x00 /* Open a port */
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#define CONFIG 0x01 /* Configure a port */
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#define MOPEN 0x02 /* Modem open (block for DCD) */
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#define CLOSE 0x03 /* Close a port */
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#define WFLUSH (0x04 | PRE_EMPTIVE) /* Write flush */
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#define RFLUSH (0x05 | PRE_EMPTIVE) /* Read flush */
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#define RESUME (0x06 | PRE_EMPTIVE) /* Resume if xoffed */
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#define SBREAK 0x07 /* Start break */
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#define EBREAK 0x08 /* End break */
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#define SUSPEND (0x09 | PRE_EMPTIVE) /* Susp op (behave as tho xoffed) */
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#define FCLOSE (0x0a | PRE_EMPTIVE) /* Force close */
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#define XPRINT 0x0b /* Xprint packet */
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#define MBIS (0x0c | PRE_EMPTIVE) /* Set modem lines */
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#define MBIC (0x0d | PRE_EMPTIVE) /* Clear modem lines */
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#define MSET (0x0e | PRE_EMPTIVE) /* Set modem lines */
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#define PCLOSE 0x0f /* Pseudo close - Leaves rx/tx enabled */
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#define MGET (0x10 | PRE_EMPTIVE) /* Force update of modem status */
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#define MEMDUMP (0x11 | PRE_EMPTIVE) /* Send back mem from addr supplied */
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#define READ_REGISTER (0x12 | PRE_EMPTIVE) /* Read CD1400 register (debug) */
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/* "Command" packets going from remote to host COMPLETE and MODEM_STATUS
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use data[4] / data[3] to indicate current state and modem status respectively
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*/
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#define COMPLETE (0x20 | PRE_EMPTIVE)
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/* Command complete */
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#define BREAK_RECEIVED (0x21 | PRE_EMPTIVE)
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/* Break received */
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#define MODEM_STATUS (0x22 | PRE_EMPTIVE)
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/* Change in modem status */
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/* "Command" packet that could go either way - handshake wake-up */
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#define HANDSHAKE (0x23 | PRE_EMPTIVE)
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/* Wake-up to HOST / RTA */
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#endif
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