99fd99f618
These have a wrap bit but again need little work to clean out. There are a couple of uglies left that want addressing in later clean up. Notably we should probably keep the local psr copy and wrap as two values. Signed-off-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
1170 lines
33 KiB
C
1170 lines
33 KiB
C
/*
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* Agere Systems Inc.
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* 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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* http://www.agere.com
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*
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*------------------------------------------------------------------------------
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*
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* et1310_rx.c - Routines used to perform data reception
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*
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*------------------------------------------------------------------------------
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*
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* SOFTWARE LICENSE
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*
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* This software is provided subject to the following terms and conditions,
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* which you should read carefully before using the software. Using this
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* software indicates your acceptance of these terms and conditions. If you do
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* not agree with these terms and conditions, do not use the software.
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*
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* Copyright © 2005 Agere Systems Inc.
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* All rights reserved.
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*
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* Redistribution and use in source or binary forms, with or without
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* modifications, are permitted provided that the following conditions are met:
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*
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* . Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following Disclaimer as comments in the code as
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* well as in the documentation and/or other materials provided with the
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* distribution.
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*
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* . Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following Disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* . Neither the name of Agere Systems Inc. nor the names of the contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* Disclaimer
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
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* INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
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* USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
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* RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
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* DAMAGE.
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*
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*/
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#include "et131x_version.h"
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#include "et131x_defs.h"
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/ctype.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/interrupt.h>
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#include <linux/in.h>
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <asm/system.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/skbuff.h>
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#include <linux/if_arp.h>
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#include <linux/ioport.h>
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#include "et1310_phy.h"
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#include "et1310_pm.h"
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#include "et1310_jagcore.h"
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#include "et131x_adapter.h"
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#include "et131x_initpci.h"
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#include "et1310_rx.h"
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void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD pMpRfd);
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/**
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* et131x_rx_dma_memory_alloc
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* @adapter: pointer to our private adapter structure
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*
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* Returns 0 on success and errno on failure (as defined in errno.h)
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*
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* Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
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* and the Packet Status Ring.
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*/
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int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
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{
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u32 i, j;
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u32 bufsize;
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u32 pktStatRingSize, FBRChunkSize;
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RX_RING_t *rx_ring;
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/* Setup some convenience pointers */
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rx_ring = (RX_RING_t *) &adapter->RxRing;
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/* Alloc memory for the lookup table */
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#ifdef USE_FBR0
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rx_ring->Fbr[0] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
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#endif
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rx_ring->Fbr[1] = kmalloc(sizeof(FBRLOOKUPTABLE), GFP_KERNEL);
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/* The first thing we will do is configure the sizes of the buffer
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* rings. These will change based on jumbo packet support. Larger
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* jumbo packets increases the size of each entry in FBR0, and the
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* number of entries in FBR0, while at the same time decreasing the
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* number of entries in FBR1.
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*
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* FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
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* entries are huge in order to accomodate a "jumbo" frame, then it
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* will have less entries. Conversely, FBR1 will now be relied upon
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* to carry more "normal" frames, thus it's entry size also increases
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* and the number of entries goes up too (since it now carries
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* "small" + "regular" packets.
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*
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* In this scheme, we try to maintain 512 entries between the two
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* rings. Also, FBR1 remains a constant size - when it's size doubles
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* the number of entries halves. FBR0 increases in size, however.
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*/
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if (adapter->RegistryJumboPacket < 2048) {
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#ifdef USE_FBR0
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rx_ring->Fbr0BufferSize = 256;
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rx_ring->Fbr0NumEntries = 512;
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#endif
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rx_ring->Fbr1BufferSize = 2048;
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rx_ring->Fbr1NumEntries = 512;
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} else if (adapter->RegistryJumboPacket < 4096) {
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#ifdef USE_FBR0
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rx_ring->Fbr0BufferSize = 512;
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rx_ring->Fbr0NumEntries = 1024;
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#endif
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rx_ring->Fbr1BufferSize = 4096;
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rx_ring->Fbr1NumEntries = 512;
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} else {
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#ifdef USE_FBR0
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rx_ring->Fbr0BufferSize = 1024;
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rx_ring->Fbr0NumEntries = 768;
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#endif
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rx_ring->Fbr1BufferSize = 16384;
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rx_ring->Fbr1NumEntries = 128;
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}
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#ifdef USE_FBR0
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adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr0NumEntries +
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adapter->RxRing.Fbr1NumEntries;
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#else
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adapter->RxRing.PsrNumEntries = adapter->RxRing.Fbr1NumEntries;
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#endif
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/* Allocate an area of memory for Free Buffer Ring 1 */
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bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
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rx_ring->pFbr1RingVa = pci_alloc_consistent(adapter->pdev,
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bufsize,
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&rx_ring->pFbr1RingPa);
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if (!rx_ring->pFbr1RingVa) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Free Buffer Ring 1\n");
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return -ENOMEM;
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}
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/* Save physical address
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*
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* NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
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* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
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* are ever returned, make sure the high part is retrieved here
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* before storing the adjusted address.
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*/
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rx_ring->Fbr1Realpa = rx_ring->pFbr1RingPa;
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/* Align Free Buffer Ring 1 on a 4K boundary */
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et131x_align_allocated_memory(adapter,
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&rx_ring->Fbr1Realpa,
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&rx_ring->Fbr1offset, 0x0FFF);
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rx_ring->pFbr1RingVa = (void *)((uint8_t *) rx_ring->pFbr1RingVa +
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rx_ring->Fbr1offset);
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#ifdef USE_FBR0
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/* Allocate an area of memory for Free Buffer Ring 0 */
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bufsize = (sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
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rx_ring->pFbr0RingVa = pci_alloc_consistent(adapter->pdev,
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bufsize,
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&rx_ring->pFbr0RingPa);
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if (!rx_ring->pFbr0RingVa) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Free Buffer Ring 0\n");
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return -ENOMEM;
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}
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/* Save physical address
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*
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* NOTE: pci_alloc_consistent(), used above to alloc DMA regions,
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* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
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* are ever returned, make sure the high part is retrieved here before
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* storing the adjusted address.
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*/
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rx_ring->Fbr0Realpa = rx_ring->pFbr0RingPa;
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/* Align Free Buffer Ring 0 on a 4K boundary */
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et131x_align_allocated_memory(adapter,
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&rx_ring->Fbr0Realpa,
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&rx_ring->Fbr0offset, 0x0FFF);
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rx_ring->pFbr0RingVa = (void *)((uint8_t *) rx_ring->pFbr0RingVa +
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rx_ring->Fbr0offset);
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#endif
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for (i = 0; i < (rx_ring->Fbr1NumEntries / FBR_CHUNKS);
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i++) {
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u64 Fbr1Offset;
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u64 Fbr1TempPa;
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u32 Fbr1Align;
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/* This code allocates an area of memory big enough for N
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* free buffers + (buffer_size - 1) so that the buffers can
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* be aligned on 4k boundaries. If each buffer were aligned
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* to a buffer_size boundary, the effect would be to double
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* the size of FBR0. By allocating N buffers at once, we
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* reduce this overhead.
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*/
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if (rx_ring->Fbr1BufferSize > 4096)
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Fbr1Align = 4096;
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else
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Fbr1Align = rx_ring->Fbr1BufferSize;
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FBRChunkSize =
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(FBR_CHUNKS * rx_ring->Fbr1BufferSize) + Fbr1Align - 1;
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rx_ring->Fbr1MemVa[i] =
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pci_alloc_consistent(adapter->pdev, FBRChunkSize,
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&rx_ring->Fbr1MemPa[i]);
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if (!rx_ring->Fbr1MemVa[i]) {
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dev_err(&adapter->pdev->dev,
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"Could not alloc memory\n");
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return -ENOMEM;
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}
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/* See NOTE in "Save Physical Address" comment above */
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Fbr1TempPa = rx_ring->Fbr1MemPa[i];
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et131x_align_allocated_memory(adapter,
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&Fbr1TempPa,
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&Fbr1Offset, (Fbr1Align - 1));
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for (j = 0; j < FBR_CHUNKS; j++) {
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u32 index = (i * FBR_CHUNKS) + j;
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/* Save the Virtual address of this index for quick
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* access later
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*/
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rx_ring->Fbr[1]->Va[index] =
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(uint8_t *) rx_ring->Fbr1MemVa[i] +
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(j * rx_ring->Fbr1BufferSize) + Fbr1Offset;
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/* now store the physical address in the descriptor
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* so the device can access it
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*/
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rx_ring->Fbr[1]->PAHigh[index] =
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(u32) (Fbr1TempPa >> 32);
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rx_ring->Fbr[1]->PALow[index] = (u32) Fbr1TempPa;
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Fbr1TempPa += rx_ring->Fbr1BufferSize;
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rx_ring->Fbr[1]->Buffer1[index] =
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rx_ring->Fbr[1]->Va[index];
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rx_ring->Fbr[1]->Buffer2[index] =
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rx_ring->Fbr[1]->Va[index] - 4;
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}
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}
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#ifdef USE_FBR0
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/* Same for FBR0 (if in use) */
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for (i = 0; i < (rx_ring->Fbr0NumEntries / FBR_CHUNKS);
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i++) {
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u64 Fbr0Offset;
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u64 Fbr0TempPa;
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FBRChunkSize = ((FBR_CHUNKS + 1) * rx_ring->Fbr0BufferSize) - 1;
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rx_ring->Fbr0MemVa[i] =
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pci_alloc_consistent(adapter->pdev, FBRChunkSize,
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&rx_ring->Fbr0MemPa[i]);
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if (!rx_ring->Fbr0MemVa[i]) {
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dev_err(&adapter->pdev->dev,
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"Could not alloc memory\n");
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return -ENOMEM;
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}
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/* See NOTE in "Save Physical Address" comment above */
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Fbr0TempPa = rx_ring->Fbr0MemPa[i];
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et131x_align_allocated_memory(adapter,
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&Fbr0TempPa,
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&Fbr0Offset,
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rx_ring->Fbr0BufferSize - 1);
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for (j = 0; j < FBR_CHUNKS; j++) {
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u32 index = (i * FBR_CHUNKS) + j;
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rx_ring->Fbr[0]->Va[index] =
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(uint8_t *) rx_ring->Fbr0MemVa[i] +
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(j * rx_ring->Fbr0BufferSize) + Fbr0Offset;
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rx_ring->Fbr[0]->PAHigh[index] =
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(u32) (Fbr0TempPa >> 32);
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rx_ring->Fbr[0]->PALow[index] = (u32) Fbr0TempPa;
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Fbr0TempPa += rx_ring->Fbr0BufferSize;
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rx_ring->Fbr[0]->Buffer1[index] =
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rx_ring->Fbr[0]->Va[index];
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rx_ring->Fbr[0]->Buffer2[index] =
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rx_ring->Fbr[0]->Va[index] - 4;
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}
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}
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#endif
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/* Allocate an area of memory for FIFO of Packet Status ring entries */
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pktStatRingSize =
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sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
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rx_ring->pPSRingVa = pci_alloc_consistent(adapter->pdev,
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pktStatRingSize,
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&rx_ring->pPSRingPa);
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if (!rx_ring->pPSRingVa) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Packet Status Ring\n");
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return -ENOMEM;
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}
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printk("PSR %lx\n", (unsigned long) rx_ring->pPSRingPa);
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/*
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* NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
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* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
|
|
* are ever returned, make sure the high part is retrieved here before
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* storing the adjusted address.
|
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*/
|
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|
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/* Allocate an area of memory for writeback of status information */
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rx_ring->pRxStatusVa = pci_alloc_consistent(adapter->pdev,
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sizeof(RX_STATUS_BLOCK_t),
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&rx_ring->pRxStatusPa);
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if (!rx_ring->pRxStatusVa) {
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dev_err(&adapter->pdev->dev,
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"Cannot alloc memory for Status Block\n");
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return -ENOMEM;
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}
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rx_ring->NumRfd = NIC_DEFAULT_NUM_RFD;
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printk("PRS %lx\n", (unsigned long)rx_ring->pRxStatusPa);
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|
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/* Recv
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* pci_pool_create initializes a lookaside list. After successful
|
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* creation, nonpaged fixed-size blocks can be allocated from and
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* freed to the lookaside list.
|
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* RFDs will be allocated from this pool.
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*/
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rx_ring->RecvLookaside = kmem_cache_create(adapter->netdev->name,
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sizeof(MP_RFD),
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0,
|
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SLAB_CACHE_DMA |
|
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SLAB_HWCACHE_ALIGN,
|
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NULL);
|
|
|
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adapter->Flags |= fMP_ADAPTER_RECV_LOOKASIDE;
|
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|
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/* The RFDs are going to be put on lists later on, so initialize the
|
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* lists now.
|
|
*/
|
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INIT_LIST_HEAD(&rx_ring->RecvList);
|
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return 0;
|
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}
|
|
|
|
/**
|
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* et131x_rx_dma_memory_free - Free all memory allocated within this module.
|
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* @adapter: pointer to our private adapter structure
|
|
*/
|
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void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
|
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{
|
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u32 index;
|
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u32 bufsize;
|
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u32 pktStatRingSize;
|
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PMP_RFD rfd;
|
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RX_RING_t *rx_ring;
|
|
|
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/* Setup some convenience pointers */
|
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rx_ring = (RX_RING_t *) &adapter->RxRing;
|
|
|
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/* Free RFDs and associated packet descriptors */
|
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WARN_ON(rx_ring->nReadyRecv != rx_ring->NumRfd);
|
|
|
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while (!list_empty(&rx_ring->RecvList)) {
|
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rfd = (MP_RFD *) list_entry(rx_ring->RecvList.next,
|
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MP_RFD, list_node);
|
|
|
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list_del(&rfd->list_node);
|
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rfd->Packet = NULL;
|
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kmem_cache_free(adapter->RxRing.RecvLookaside, rfd);
|
|
}
|
|
|
|
/* Free Free Buffer Ring 1 */
|
|
if (rx_ring->pFbr1RingVa) {
|
|
/* First the packet memory */
|
|
for (index = 0; index <
|
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(rx_ring->Fbr1NumEntries / FBR_CHUNKS); index++) {
|
|
if (rx_ring->Fbr1MemVa[index]) {
|
|
u32 Fbr1Align;
|
|
|
|
if (rx_ring->Fbr1BufferSize > 4096)
|
|
Fbr1Align = 4096;
|
|
else
|
|
Fbr1Align = rx_ring->Fbr1BufferSize;
|
|
|
|
bufsize =
|
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(rx_ring->Fbr1BufferSize * FBR_CHUNKS) +
|
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Fbr1Align - 1;
|
|
|
|
pci_free_consistent(adapter->pdev,
|
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bufsize,
|
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rx_ring->Fbr1MemVa[index],
|
|
rx_ring->Fbr1MemPa[index]);
|
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|
|
rx_ring->Fbr1MemVa[index] = NULL;
|
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}
|
|
}
|
|
|
|
/* Now the FIFO itself */
|
|
rx_ring->pFbr1RingVa = (void *)((uint8_t *)
|
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rx_ring->pFbr1RingVa - rx_ring->Fbr1offset);
|
|
|
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bufsize =
|
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(sizeof(FBR_DESC_t) * rx_ring->Fbr1NumEntries) + 0xfff;
|
|
|
|
pci_free_consistent(adapter->pdev,
|
|
bufsize,
|
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rx_ring->pFbr1RingVa, rx_ring->pFbr1RingPa);
|
|
|
|
rx_ring->pFbr1RingVa = NULL;
|
|
}
|
|
|
|
#ifdef USE_FBR0
|
|
/* Now the same for Free Buffer Ring 0 */
|
|
if (rx_ring->pFbr0RingVa) {
|
|
/* First the packet memory */
|
|
for (index = 0; index <
|
|
(rx_ring->Fbr0NumEntries / FBR_CHUNKS); index++) {
|
|
if (rx_ring->Fbr0MemVa[index]) {
|
|
bufsize =
|
|
(rx_ring->Fbr0BufferSize *
|
|
(FBR_CHUNKS + 1)) - 1;
|
|
|
|
pci_free_consistent(adapter->pdev,
|
|
bufsize,
|
|
rx_ring->Fbr0MemVa[index],
|
|
rx_ring->Fbr0MemPa[index]);
|
|
|
|
rx_ring->Fbr0MemVa[index] = NULL;
|
|
}
|
|
}
|
|
|
|
/* Now the FIFO itself */
|
|
rx_ring->pFbr0RingVa = (void *)((uint8_t *)
|
|
rx_ring->pFbr0RingVa - rx_ring->Fbr0offset);
|
|
|
|
bufsize =
|
|
(sizeof(FBR_DESC_t) * rx_ring->Fbr0NumEntries) + 0xfff;
|
|
|
|
pci_free_consistent(adapter->pdev,
|
|
bufsize,
|
|
rx_ring->pFbr0RingVa, rx_ring->pFbr0RingPa);
|
|
|
|
rx_ring->pFbr0RingVa = NULL;
|
|
}
|
|
#endif
|
|
|
|
/* Free Packet Status Ring */
|
|
if (rx_ring->pPSRingVa) {
|
|
pktStatRingSize =
|
|
sizeof(PKT_STAT_DESC_t) * adapter->RxRing.PsrNumEntries;
|
|
|
|
pci_free_consistent(adapter->pdev, pktStatRingSize,
|
|
rx_ring->pPSRingVa, rx_ring->pPSRingPa);
|
|
|
|
rx_ring->pPSRingVa = NULL;
|
|
}
|
|
|
|
/* Free area of memory for the writeback of status information */
|
|
if (rx_ring->pRxStatusVa) {
|
|
pci_free_consistent(adapter->pdev,
|
|
sizeof(RX_STATUS_BLOCK_t),
|
|
rx_ring->pRxStatusVa, rx_ring->pRxStatusPa);
|
|
|
|
rx_ring->pRxStatusVa = NULL;
|
|
}
|
|
|
|
/* Free receive buffer pool */
|
|
|
|
/* Free receive packet pool */
|
|
|
|
/* Destroy the lookaside (RFD) pool */
|
|
if (adapter->Flags & fMP_ADAPTER_RECV_LOOKASIDE) {
|
|
kmem_cache_destroy(rx_ring->RecvLookaside);
|
|
adapter->Flags &= ~fMP_ADAPTER_RECV_LOOKASIDE;
|
|
}
|
|
|
|
/* Free the FBR Lookup Table */
|
|
#ifdef USE_FBR0
|
|
kfree(rx_ring->Fbr[0]);
|
|
#endif
|
|
|
|
kfree(rx_ring->Fbr[1]);
|
|
|
|
/* Reset Counters */
|
|
rx_ring->nReadyRecv = 0;
|
|
}
|
|
|
|
/**
|
|
* et131x_init_recv - Initialize receive data structures.
|
|
* @adapter: pointer to our private adapter structure
|
|
*
|
|
* Returns 0 on success and errno on failure (as defined in errno.h)
|
|
*/
|
|
int et131x_init_recv(struct et131x_adapter *adapter)
|
|
{
|
|
int status = -ENOMEM;
|
|
PMP_RFD rfd = NULL;
|
|
u32 rfdct;
|
|
u32 numrfd = 0;
|
|
RX_RING_t *rx_ring = NULL;
|
|
|
|
/* Setup some convenience pointers */
|
|
rx_ring = (RX_RING_t *) &adapter->RxRing;
|
|
|
|
/* Setup each RFD */
|
|
for (rfdct = 0; rfdct < rx_ring->NumRfd; rfdct++) {
|
|
rfd = (MP_RFD *) kmem_cache_alloc(rx_ring->RecvLookaside,
|
|
GFP_ATOMIC | GFP_DMA);
|
|
|
|
if (!rfd) {
|
|
dev_err(&adapter->pdev->dev,
|
|
"Couldn't alloc RFD out of kmem_cache\n");
|
|
status = -ENOMEM;
|
|
continue;
|
|
}
|
|
|
|
rfd->Packet = NULL;
|
|
|
|
/* Add this RFD to the RecvList */
|
|
list_add_tail(&rfd->list_node, &rx_ring->RecvList);
|
|
|
|
/* Increment both the available RFD's, and the total RFD's. */
|
|
rx_ring->nReadyRecv++;
|
|
numrfd++;
|
|
}
|
|
|
|
if (numrfd > NIC_MIN_NUM_RFD)
|
|
status = 0;
|
|
|
|
rx_ring->NumRfd = numrfd;
|
|
|
|
if (status != 0) {
|
|
kmem_cache_free(rx_ring->RecvLookaside, rfd);
|
|
dev_err(&adapter->pdev->dev,
|
|
"Allocation problems in et131x_init_recv\n");
|
|
}
|
|
return status;
|
|
}
|
|
|
|
/**
|
|
* ConfigRxDmaRegs - Start of Rx_DMA init sequence
|
|
* @etdev: pointer to our adapter structure
|
|
*/
|
|
void ConfigRxDmaRegs(struct et131x_adapter *etdev)
|
|
{
|
|
struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma;
|
|
struct _rx_ring_t *rx_local = &etdev->RxRing;
|
|
PFBR_DESC_t fbr_entry;
|
|
u32 entry;
|
|
u32 psr_num_des;
|
|
unsigned long flags;
|
|
|
|
/* Halt RXDMA to perform the reconfigure. */
|
|
et131x_rx_dma_disable(etdev);
|
|
|
|
/* Load the completion writeback physical address
|
|
*
|
|
* NOTE : pci_alloc_consistent(), used above to alloc DMA regions,
|
|
* ALWAYS returns SAC (32-bit) addresses. If DAC (64-bit) addresses
|
|
* are ever returned, make sure the high part is retrieved here
|
|
* before storing the adjusted address.
|
|
*/
|
|
writel((u32) ((u64)rx_local->pRxStatusPa >> 32),
|
|
&rx_dma->dma_wb_base_hi);
|
|
writel((u32) rx_local->pRxStatusPa, &rx_dma->dma_wb_base_lo);
|
|
|
|
memset(rx_local->pRxStatusVa, 0, sizeof(RX_STATUS_BLOCK_t));
|
|
|
|
/* Set the address and parameters of the packet status ring into the
|
|
* 1310's registers
|
|
*/
|
|
writel((u32) ((u64)rx_local->pPSRingPa >> 32),
|
|
&rx_dma->psr_base_hi);
|
|
writel((u32) rx_local->pPSRingPa, &rx_dma->psr_base_lo);
|
|
writel(rx_local->PsrNumEntries - 1, &rx_dma->psr_num_des);
|
|
writel(0, &rx_dma->psr_full_offset);
|
|
|
|
psr_num_des = readl(&rx_dma->psr_num_des) & 0xFFF;
|
|
writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
|
|
&rx_dma->psr_min_des);
|
|
|
|
spin_lock_irqsave(&etdev->RcvLock, flags);
|
|
|
|
/* These local variables track the PSR in the adapter structure */
|
|
rx_local->local_psr_full = 0;
|
|
|
|
/* Now's the best time to initialize FBR1 contents */
|
|
fbr_entry = (PFBR_DESC_t) rx_local->pFbr1RingVa;
|
|
for (entry = 0; entry < rx_local->Fbr1NumEntries; entry++) {
|
|
fbr_entry->addr_hi = rx_local->Fbr[1]->PAHigh[entry];
|
|
fbr_entry->addr_lo = rx_local->Fbr[1]->PALow[entry];
|
|
fbr_entry->word2.bits.bi = entry;
|
|
fbr_entry++;
|
|
}
|
|
|
|
/* Set the address and parameters of Free buffer ring 1 (and 0 if
|
|
* required) into the 1310's registers
|
|
*/
|
|
writel((u32) (rx_local->Fbr1Realpa >> 32), &rx_dma->fbr1_base_hi);
|
|
writel((u32) rx_local->Fbr1Realpa, &rx_dma->fbr1_base_lo);
|
|
writel(rx_local->Fbr1NumEntries - 1, &rx_dma->fbr1_num_des);
|
|
writel(ET_DMA10_WRAP, &rx_dma->fbr1_full_offset);
|
|
|
|
/* This variable tracks the free buffer ring 1 full position, so it
|
|
* has to match the above.
|
|
*/
|
|
rx_local->local_Fbr1_full = ET_DMA10_WRAP;
|
|
writel(((rx_local->Fbr1NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
|
|
&rx_dma->fbr1_min_des);
|
|
|
|
#ifdef USE_FBR0
|
|
/* Now's the best time to initialize FBR0 contents */
|
|
fbr_entry = (PFBR_DESC_t) rx_local->pFbr0RingVa;
|
|
for (entry = 0; entry < rx_local->Fbr0NumEntries; entry++) {
|
|
fbr_entry->addr_hi = rx_local->Fbr[0]->PAHigh[entry];
|
|
fbr_entry->addr_lo = rx_local->Fbr[0]->PALow[entry];
|
|
fbr_entry->word2.bits.bi = entry;
|
|
fbr_entry++;
|
|
}
|
|
|
|
writel((u32) (rx_local->Fbr0Realpa >> 32), &rx_dma->fbr0_base_hi);
|
|
writel((u32) rx_local->Fbr0Realpa, &rx_dma->fbr0_base_lo);
|
|
writel(rx_local->Fbr0NumEntries - 1, &rx_dma->fbr0_num_des);
|
|
writel(ET_DMA10_WRAP, &rx_dma->fbr0_full_offset);
|
|
|
|
/* This variable tracks the free buffer ring 0 full position, so it
|
|
* has to match the above.
|
|
*/
|
|
rx_local->local_Fbr0_full = ET_DMA10_WRAP;
|
|
writel(((rx_local->Fbr0NumEntries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
|
|
&rx_dma->fbr0_min_des);
|
|
#endif
|
|
|
|
/* Program the number of packets we will receive before generating an
|
|
* interrupt.
|
|
* For version B silicon, this value gets updated once autoneg is
|
|
*complete.
|
|
*/
|
|
writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
|
|
|
|
/* The "time_done" is not working correctly to coalesce interrupts
|
|
* after a given time period, but rather is giving us an interrupt
|
|
* regardless of whether we have received packets.
|
|
* This value gets updated once autoneg is complete.
|
|
*/
|
|
writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
|
|
|
|
spin_unlock_irqrestore(&etdev->RcvLock, flags);
|
|
}
|
|
|
|
/**
|
|
* SetRxDmaTimer - Set the heartbeat timer according to line rate.
|
|
* @etdev: pointer to our adapter structure
|
|
*/
|
|
void SetRxDmaTimer(struct et131x_adapter *etdev)
|
|
{
|
|
/* For version B silicon, we do not use the RxDMA timer for 10 and 100
|
|
* Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
|
|
*/
|
|
if ((etdev->linkspeed == TRUEPHY_SPEED_100MBPS) ||
|
|
(etdev->linkspeed == TRUEPHY_SPEED_10MBPS)) {
|
|
writel(0, &etdev->regs->rxdma.max_pkt_time);
|
|
writel(1, &etdev->regs->rxdma.num_pkt_done);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* et131x_rx_dma_disable - Stop of Rx_DMA on the ET1310
|
|
* @etdev: pointer to our adapter structure
|
|
*/
|
|
void et131x_rx_dma_disable(struct et131x_adapter *etdev)
|
|
{
|
|
RXDMA_CSR_t csr;
|
|
|
|
/* Setup the receive dma configuration register */
|
|
writel(0x00002001, &etdev->regs->rxdma.csr.value);
|
|
csr.value = readl(&etdev->regs->rxdma.csr.value);
|
|
if (csr.bits.halt_status != 1) {
|
|
udelay(5);
|
|
csr.value = readl(&etdev->regs->rxdma.csr.value);
|
|
if (csr.bits.halt_status != 1)
|
|
dev_err(&etdev->pdev->dev,
|
|
"RX Dma failed to enter halt state. CSR 0x%08x\n",
|
|
csr.value);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* et131x_rx_dma_enable - re-start of Rx_DMA on the ET1310.
|
|
* @etdev: pointer to our adapter structure
|
|
*/
|
|
void et131x_rx_dma_enable(struct et131x_adapter *etdev)
|
|
{
|
|
/* Setup the receive dma configuration register for normal operation */
|
|
RXDMA_CSR_t csr = { 0 };
|
|
|
|
csr.bits.fbr1_enable = 1;
|
|
if (etdev->RxRing.Fbr1BufferSize == 4096)
|
|
csr.bits.fbr1_size = 1;
|
|
else if (etdev->RxRing.Fbr1BufferSize == 8192)
|
|
csr.bits.fbr1_size = 2;
|
|
else if (etdev->RxRing.Fbr1BufferSize == 16384)
|
|
csr.bits.fbr1_size = 3;
|
|
#ifdef USE_FBR0
|
|
csr.bits.fbr0_enable = 1;
|
|
if (etdev->RxRing.Fbr0BufferSize == 256)
|
|
csr.bits.fbr0_size = 1;
|
|
else if (etdev->RxRing.Fbr0BufferSize == 512)
|
|
csr.bits.fbr0_size = 2;
|
|
else if (etdev->RxRing.Fbr0BufferSize == 1024)
|
|
csr.bits.fbr0_size = 3;
|
|
#endif
|
|
writel(csr.value, &etdev->regs->rxdma.csr.value);
|
|
|
|
csr.value = readl(&etdev->regs->rxdma.csr.value);
|
|
if (csr.bits.halt_status != 0) {
|
|
udelay(5);
|
|
csr.value = readl(&etdev->regs->rxdma.csr.value);
|
|
if (csr.bits.halt_status != 0) {
|
|
dev_err(&etdev->pdev->dev,
|
|
"RX Dma failed to exit halt state. CSR 0x%08x\n",
|
|
csr.value);
|
|
}
|
|
}
|
|
}
|
|
|
|
/**
|
|
* nic_rx_pkts - Checks the hardware for available packets
|
|
* @etdev: pointer to our adapter
|
|
*
|
|
* Returns rfd, a pointer to our MPRFD.
|
|
*
|
|
* Checks the hardware for available packets, using completion ring
|
|
* If packets are available, it gets an RFD from the RecvList, attaches
|
|
* the packet to it, puts the RFD in the RecvPendList, and also returns
|
|
* the pointer to the RFD.
|
|
*/
|
|
PMP_RFD nic_rx_pkts(struct et131x_adapter *etdev)
|
|
{
|
|
struct _rx_ring_t *rx_local = &etdev->RxRing;
|
|
PRX_STATUS_BLOCK_t status;
|
|
PPKT_STAT_DESC_t psr;
|
|
PMP_RFD rfd;
|
|
u32 i;
|
|
uint8_t *buf;
|
|
unsigned long flags;
|
|
struct list_head *element;
|
|
uint8_t rindex;
|
|
uint16_t bindex;
|
|
u32 len;
|
|
PKT_STAT_DESC_WORD0_t Word0;
|
|
|
|
/* RX Status block is written by the DMA engine prior to every
|
|
* interrupt. It contains the next to be used entry in the Packet
|
|
* Status Ring, and also the two Free Buffer rings.
|
|
*/
|
|
status = (PRX_STATUS_BLOCK_t) rx_local->pRxStatusVa;
|
|
|
|
/* FIXME: tidy later when conversions complete */
|
|
if (status->Word1.bits.PSRoffset ==
|
|
(rx_local->local_psr_full & 0xFFF) &&
|
|
status->Word1.bits.PSRwrap ==
|
|
((rx_local->local_psr_full >> 12) & 1)) {
|
|
/* Looks like this ring is not updated yet */
|
|
return NULL;
|
|
}
|
|
|
|
/* The packet status ring indicates that data is available. */
|
|
psr = (PPKT_STAT_DESC_t) (rx_local->pPSRingVa) +
|
|
(rx_local->local_psr_full & 0xFFF);
|
|
|
|
/* Grab any information that is required once the PSR is
|
|
* advanced, since we can no longer rely on the memory being
|
|
* accurate
|
|
*/
|
|
len = psr->word1.bits.length;
|
|
rindex = (uint8_t) psr->word1.bits.ri;
|
|
bindex = (uint16_t) psr->word1.bits.bi;
|
|
Word0 = psr->word0;
|
|
|
|
/* Indicate that we have used this PSR entry. */
|
|
/* FIXME wrap 12 */
|
|
rx_local->local_psr_full = (rx_local->local_psr_full + 1) & 0xFFF;
|
|
if (rx_local->local_psr_full > rx_local->PsrNumEntries - 1) {
|
|
/* Clear psr full and toggle the wrap bit */
|
|
rx_local->local_psr_full &= 0xFFF;
|
|
rx_local->local_psr_full ^= 0x1000;
|
|
}
|
|
|
|
writel(rx_local->local_psr_full,
|
|
&etdev->regs->rxdma.psr_full_offset);
|
|
|
|
#ifndef USE_FBR0
|
|
if (rindex != 1) {
|
|
return NULL;
|
|
}
|
|
#endif
|
|
|
|
#ifdef USE_FBR0
|
|
if (rindex > 1 ||
|
|
(rindex == 0 &&
|
|
bindex > rx_local->Fbr0NumEntries - 1) ||
|
|
(rindex == 1 &&
|
|
bindex > rx_local->Fbr1NumEntries - 1))
|
|
#else
|
|
if (rindex != 1 ||
|
|
bindex > rx_local->Fbr1NumEntries - 1)
|
|
#endif
|
|
{
|
|
/* Illegal buffer or ring index cannot be used by S/W*/
|
|
dev_err(&etdev->pdev->dev,
|
|
"NICRxPkts PSR Entry %d indicates "
|
|
"length of %d and/or bad bi(%d)\n",
|
|
rx_local->local_psr_full & 0xFFF,
|
|
len, bindex);
|
|
return NULL;
|
|
}
|
|
|
|
/* Get and fill the RFD. */
|
|
spin_lock_irqsave(&etdev->RcvLock, flags);
|
|
|
|
rfd = NULL;
|
|
element = rx_local->RecvList.next;
|
|
rfd = (PMP_RFD) list_entry(element, MP_RFD, list_node);
|
|
|
|
if (rfd == NULL) {
|
|
spin_unlock_irqrestore(&etdev->RcvLock, flags);
|
|
return NULL;
|
|
}
|
|
|
|
list_del(&rfd->list_node);
|
|
rx_local->nReadyRecv--;
|
|
|
|
spin_unlock_irqrestore(&etdev->RcvLock, flags);
|
|
|
|
rfd->bufferindex = bindex;
|
|
rfd->ringindex = rindex;
|
|
|
|
/* In V1 silicon, there is a bug which screws up filtering of
|
|
* runt packets. Therefore runt packet filtering is disabled
|
|
* in the MAC and the packets are dropped here. They are
|
|
* also counted here.
|
|
*/
|
|
if (len < (NIC_MIN_PACKET_SIZE + 4)) {
|
|
etdev->Stats.other_errors++;
|
|
len = 0;
|
|
}
|
|
|
|
if (len) {
|
|
if (etdev->ReplicaPhyLoopbk == 1) {
|
|
buf = rx_local->Fbr[rindex]->Va[bindex];
|
|
|
|
if (memcmp(&buf[6], &etdev->CurrentAddress[0],
|
|
ETH_ALEN) == 0) {
|
|
if (memcmp(&buf[42], "Replica packet",
|
|
ETH_HLEN)) {
|
|
etdev->ReplicaPhyLoopbkPF = 1;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* Determine if this is a multicast packet coming in */
|
|
if ((Word0.value & ALCATEL_MULTICAST_PKT) &&
|
|
!(Word0.value & ALCATEL_BROADCAST_PKT)) {
|
|
/* Promiscuous mode and Multicast mode are
|
|
* not mutually exclusive as was first
|
|
* thought. I guess Promiscuous is just
|
|
* considered a super-set of the other
|
|
* filters. Generally filter is 0x2b when in
|
|
* promiscuous mode.
|
|
*/
|
|
if ((etdev->PacketFilter & ET131X_PACKET_TYPE_MULTICAST)
|
|
&& !(etdev->PacketFilter & ET131X_PACKET_TYPE_PROMISCUOUS)
|
|
&& !(etdev->PacketFilter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
|
|
buf = rx_local->Fbr[rindex]->
|
|
Va[bindex];
|
|
|
|
/* Loop through our list to see if the
|
|
* destination address of this packet
|
|
* matches one in our list.
|
|
*/
|
|
for (i = 0;
|
|
i < etdev->MCAddressCount;
|
|
i++) {
|
|
if (buf[0] ==
|
|
etdev->MCList[i][0]
|
|
&& buf[1] ==
|
|
etdev->MCList[i][1]
|
|
&& buf[2] ==
|
|
etdev->MCList[i][2]
|
|
&& buf[3] ==
|
|
etdev->MCList[i][3]
|
|
&& buf[4] ==
|
|
etdev->MCList[i][4]
|
|
&& buf[5] ==
|
|
etdev->MCList[i][5]) {
|
|
break;
|
|
}
|
|
}
|
|
|
|
/* If our index is equal to the number
|
|
* of Multicast address we have, then
|
|
* this means we did not find this
|
|
* packet's matching address in our
|
|
* list. Set the PacketSize to zero,
|
|
* so we free our RFD when we return
|
|
* from this function.
|
|
*/
|
|
if (i == etdev->MCAddressCount)
|
|
len = 0;
|
|
}
|
|
|
|
if (len > 0)
|
|
etdev->Stats.multircv++;
|
|
} else if (Word0.value & ALCATEL_BROADCAST_PKT)
|
|
etdev->Stats.brdcstrcv++;
|
|
else
|
|
/* Not sure what this counter measures in
|
|
* promiscuous mode. Perhaps we should check
|
|
* the MAC address to see if it is directed
|
|
* to us in promiscuous mode.
|
|
*/
|
|
etdev->Stats.unircv++;
|
|
}
|
|
|
|
if (len > 0) {
|
|
struct sk_buff *skb = NULL;
|
|
|
|
/* rfd->PacketSize = len - 4; */
|
|
rfd->PacketSize = len;
|
|
|
|
skb = dev_alloc_skb(rfd->PacketSize + 2);
|
|
if (!skb) {
|
|
dev_err(&etdev->pdev->dev,
|
|
"Couldn't alloc an SKB for Rx\n");
|
|
return NULL;
|
|
}
|
|
|
|
etdev->net_stats.rx_bytes += rfd->PacketSize;
|
|
|
|
memcpy(skb_put(skb, rfd->PacketSize),
|
|
rx_local->Fbr[rindex]->Va[bindex],
|
|
rfd->PacketSize);
|
|
|
|
skb->dev = etdev->netdev;
|
|
skb->protocol = eth_type_trans(skb, etdev->netdev);
|
|
skb->ip_summed = CHECKSUM_NONE;
|
|
|
|
netif_rx(skb);
|
|
} else {
|
|
rfd->PacketSize = 0;
|
|
}
|
|
|
|
nic_return_rfd(etdev, rfd);
|
|
return rfd;
|
|
}
|
|
|
|
/**
|
|
* et131x_reset_recv - Reset the receive list
|
|
* @etdev: pointer to our adapter
|
|
*
|
|
* Assumption, Rcv spinlock has been acquired.
|
|
*/
|
|
void et131x_reset_recv(struct et131x_adapter *etdev)
|
|
{
|
|
WARN_ON(list_empty(&etdev->RxRing.RecvList));
|
|
|
|
}
|
|
|
|
/**
|
|
* et131x_handle_recv_interrupt - Interrupt handler for receive processing
|
|
* @etdev: pointer to our adapter
|
|
*
|
|
* Assumption, Rcv spinlock has been acquired.
|
|
*/
|
|
void et131x_handle_recv_interrupt(struct et131x_adapter *etdev)
|
|
{
|
|
PMP_RFD rfd = NULL;
|
|
u32 count = 0;
|
|
bool done = true;
|
|
|
|
/* Process up to available RFD's */
|
|
while (count < NUM_PACKETS_HANDLED) {
|
|
if (list_empty(&etdev->RxRing.RecvList)) {
|
|
WARN_ON(etdev->RxRing.nReadyRecv != 0);
|
|
done = false;
|
|
break;
|
|
}
|
|
|
|
rfd = nic_rx_pkts(etdev);
|
|
|
|
if (rfd == NULL)
|
|
break;
|
|
|
|
/* Do not receive any packets until a filter has been set.
|
|
* Do not receive any packets until we have link.
|
|
* If length is zero, return the RFD in order to advance the
|
|
* Free buffer ring.
|
|
*/
|
|
if (!etdev->PacketFilter ||
|
|
!(etdev->Flags & fMP_ADAPTER_LINK_DETECTION) ||
|
|
rfd->PacketSize == 0) {
|
|
continue;
|
|
}
|
|
|
|
/* Increment the number of packets we received */
|
|
etdev->Stats.ipackets++;
|
|
|
|
/* Set the status on the packet, either resources or success */
|
|
if (etdev->RxRing.nReadyRecv < RFD_LOW_WATER_MARK) {
|
|
dev_warn(&etdev->pdev->dev,
|
|
"RFD's are running out\n");
|
|
}
|
|
count++;
|
|
}
|
|
|
|
if (count == NUM_PACKETS_HANDLED || !done) {
|
|
etdev->RxRing.UnfinishedReceives = true;
|
|
writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
|
|
&etdev->regs->global.watchdog_timer);
|
|
} else
|
|
/* Watchdog timer will disable itself if appropriate. */
|
|
etdev->RxRing.UnfinishedReceives = false;
|
|
}
|
|
|
|
static inline u32 bump_fbr(u32 *fbr, u32 limit)
|
|
{
|
|
u32 v = *fbr;
|
|
v++;
|
|
/* This works for all cases where limit < 1024. The 1023 case
|
|
works because 1023++ is 1024 which means the if condition is not
|
|
taken but the carry of the bit into the wrap bit toggles the wrap
|
|
value correctly */
|
|
if ((v & ET_DMA10_MASK) > limit) {
|
|
v &= ~ET_DMA10_MASK;
|
|
v ^= ET_DMA10_WRAP;
|
|
}
|
|
/* For the 1023 case */
|
|
v &= (ET_DMA10_MASK|ET_DMA10_WRAP);
|
|
*fbr = v;
|
|
return v;
|
|
}
|
|
|
|
/**
|
|
* NICReturnRFD - Recycle a RFD and put it back onto the receive list
|
|
* @etdev: pointer to our adapter
|
|
* @rfd: pointer to the RFD
|
|
*/
|
|
void nic_return_rfd(struct et131x_adapter *etdev, PMP_RFD rfd)
|
|
{
|
|
struct _rx_ring_t *rx_local = &etdev->RxRing;
|
|
struct _RXDMA_t __iomem *rx_dma = &etdev->regs->rxdma;
|
|
uint16_t bi = rfd->bufferindex;
|
|
uint8_t ri = rfd->ringindex;
|
|
unsigned long flags;
|
|
|
|
/* We don't use any of the OOB data besides status. Otherwise, we
|
|
* need to clean up OOB data
|
|
*/
|
|
if (
|
|
#ifdef USE_FBR0
|
|
(ri == 0 && bi < rx_local->Fbr0NumEntries) ||
|
|
#endif
|
|
(ri == 1 && bi < rx_local->Fbr1NumEntries)) {
|
|
spin_lock_irqsave(&etdev->FbrLock, flags);
|
|
|
|
if (ri == 1) {
|
|
PFBR_DESC_t next =
|
|
(PFBR_DESC_t) (rx_local->pFbr1RingVa) +
|
|
INDEX10(rx_local->local_Fbr1_full);
|
|
|
|
/* Handle the Free Buffer Ring advancement here. Write
|
|
* the PA / Buffer Index for the returned buffer into
|
|
* the oldest (next to be freed)FBR entry
|
|
*/
|
|
next->addr_hi = rx_local->Fbr[1]->PAHigh[bi];
|
|
next->addr_lo = rx_local->Fbr[1]->PALow[bi];
|
|
next->word2.value = bi;
|
|
|
|
writel(bump_fbr(&rx_local->local_Fbr1_full,
|
|
rx_local->Fbr1NumEntries - 1),
|
|
&rx_dma->fbr1_full_offset);
|
|
}
|
|
#ifdef USE_FBR0
|
|
else {
|
|
PFBR_DESC_t next =
|
|
(PFBR_DESC_t) rx_local->pFbr0RingVa +
|
|
INDEX10(rx_local->local_Fbr0_full);
|
|
|
|
/* Handle the Free Buffer Ring advancement here. Write
|
|
* the PA / Buffer Index for the returned buffer into
|
|
* the oldest (next to be freed) FBR entry
|
|
*/
|
|
next->addr_hi = rx_local->Fbr[0]->PAHigh[bi];
|
|
next->addr_lo = rx_local->Fbr[0]->PALow[bi];
|
|
next->word2.value = bi;
|
|
|
|
writel(bump_fbr(&rx_local->local_Fbr0_full,
|
|
rx_local->Fbr0NumEntries - 1),
|
|
&rx_dma->fbr0_full_offset);
|
|
}
|
|
#endif
|
|
spin_unlock_irqrestore(&etdev->FbrLock, flags);
|
|
} else {
|
|
dev_err(&etdev->pdev->dev,
|
|
"NICReturnRFD illegal Buffer Index returned\n");
|
|
}
|
|
|
|
/* The processing on this RFD is done, so put it back on the tail of
|
|
* our list
|
|
*/
|
|
spin_lock_irqsave(&etdev->RcvLock, flags);
|
|
list_add_tail(&rfd->list_node, &rx_local->RecvList);
|
|
rx_local->nReadyRecv++;
|
|
spin_unlock_irqrestore(&etdev->RcvLock, flags);
|
|
|
|
WARN_ON(rx_local->nReadyRecv > rx_local->NumRfd);
|
|
}
|