This means "DMA Read returns" can bypass "MMIO Writes".
Violating the PCI specs in this case improves outbound DMA "flows"
and is currently not required by any drivers.
This is NOT a new behavior. Previous chipsets did this
already and I believe ZX1 PDC was already setting this
for hpux. I just want to further document the behavior.
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Signed-off-by: Kyle McMartin <kyle@parisc-linux.org>
b312c33e36