8ceee660aa
The driver supports the 10Xpress PHY and XFP modules on our reference designs SFE4001 and SFE4002 and the SMC models SMC10GPCIe-XFP and SMC10GPCIe-10BT. Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Jeff Garzik <jgarzik@redhat.com>
586 lines
16 KiB
C
586 lines
16 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2008 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/delay.h>
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#include "net_driver.h"
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#include "efx.h"
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#include "falcon.h"
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#include "falcon_hwdefs.h"
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#include "falcon_io.h"
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#include "mac.h"
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#include "gmii.h"
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#include "mdio_10g.h"
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#include "phy.h"
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#include "boards.h"
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#include "workarounds.h"
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/**************************************************************************
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*
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* MAC register access
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*
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**************************************************************************/
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/* Offset of an XMAC register within Falcon */
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#define FALCON_XMAC_REG(mac_reg) \
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(FALCON_XMAC_REGBANK + ((mac_reg) * FALCON_XMAC_REG_SIZE))
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void falcon_xmac_writel(struct efx_nic *efx,
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efx_dword_t *value, unsigned int mac_reg)
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{
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efx_oword_t temp;
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EFX_POPULATE_OWORD_1(temp, MAC_DATA, EFX_DWORD_FIELD(*value, MAC_DATA));
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falcon_write(efx, &temp, FALCON_XMAC_REG(mac_reg));
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}
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void falcon_xmac_readl(struct efx_nic *efx,
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efx_dword_t *value, unsigned int mac_reg)
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{
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efx_oword_t temp;
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falcon_read(efx, &temp, FALCON_XMAC_REG(mac_reg));
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EFX_POPULATE_DWORD_1(*value, MAC_DATA, EFX_OWORD_FIELD(temp, MAC_DATA));
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}
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/**************************************************************************
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*
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* MAC operations
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*
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*************************************************************************/
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static int falcon_reset_xmac(struct efx_nic *efx)
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{
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efx_dword_t reg;
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int count;
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EFX_POPULATE_DWORD_1(reg, XM_CORE_RST, 1);
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falcon_xmac_writel(efx, ®, XM_GLB_CFG_REG_MAC);
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for (count = 0; count < 10000; count++) { /* wait upto 100ms */
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falcon_xmac_readl(efx, ®, XM_GLB_CFG_REG_MAC);
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if (EFX_DWORD_FIELD(reg, XM_CORE_RST) == 0)
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return 0;
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udelay(10);
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}
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EFX_ERR(efx, "timed out waiting for XMAC core reset\n");
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return -ETIMEDOUT;
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}
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/* Configure the XAUI driver that is an output from Falcon */
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static void falcon_setup_xaui(struct efx_nic *efx)
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{
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efx_dword_t sdctl, txdrv;
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/* Move the XAUI into low power, unless there is no PHY, in
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* which case the XAUI will have to drive a cable. */
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if (efx->phy_type == PHY_TYPE_NONE)
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return;
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falcon_xmac_readl(efx, &sdctl, XX_SD_CTL_REG_MAC);
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EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVD, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_LODRVD, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVC, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_LODRVC, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVB, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_LODRVB, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_HIDRVA, XX_SD_CTL_DRV_DEFAULT);
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EFX_SET_DWORD_FIELD(sdctl, XX_LODRVA, XX_SD_CTL_DRV_DEFAULT);
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falcon_xmac_writel(efx, &sdctl, XX_SD_CTL_REG_MAC);
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EFX_POPULATE_DWORD_8(txdrv,
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XX_DEQD, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQC, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQB, XX_TXDRV_DEQ_DEFAULT,
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XX_DEQA, XX_TXDRV_DEQ_DEFAULT,
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XX_DTXD, XX_TXDRV_DTX_DEFAULT,
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XX_DTXC, XX_TXDRV_DTX_DEFAULT,
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XX_DTXB, XX_TXDRV_DTX_DEFAULT,
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XX_DTXA, XX_TXDRV_DTX_DEFAULT);
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falcon_xmac_writel(efx, &txdrv, XX_TXDRV_CTL_REG_MAC);
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}
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static void falcon_hold_xaui_in_rst(struct efx_nic *efx)
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{
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efx_dword_t reg;
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EFX_ZERO_DWORD(reg);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1);
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EFX_SET_DWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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}
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static int _falcon_reset_xaui_a(struct efx_nic *efx)
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{
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efx_dword_t reg;
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falcon_hold_xaui_in_rst(efx);
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falcon_xmac_readl(efx, ®, XX_PWR_RST_REG_MAC);
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/* Follow the RAMBUS XAUI data reset sequencing
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* Channels A and B first: power down, reset PLL, reset, clear
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*/
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNA_EN, 0);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNB_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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EFX_SET_DWORD_FIELD(reg, XX_RSTPLLAB_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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EFX_SET_DWORD_FIELD(reg, XX_RESETA_EN, 0);
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EFX_SET_DWORD_FIELD(reg, XX_RESETB_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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/* Channels C and D: power down, reset PLL, reset, clear */
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EFX_SET_DWORD_FIELD(reg, XX_PWRDNC_EN, 0);
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EFX_SET_DWORD_FIELD(reg, XX_PWRDND_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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EFX_SET_DWORD_FIELD(reg, XX_RSTPLLCD_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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EFX_SET_DWORD_FIELD(reg, XX_RESETC_EN, 0);
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EFX_SET_DWORD_FIELD(reg, XX_RESETD_EN, 0);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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/* Setup XAUI */
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falcon_setup_xaui(efx);
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udelay(10);
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/* Take XGXS out of reset */
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EFX_ZERO_DWORD(reg);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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udelay(10);
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return 0;
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}
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static int _falcon_reset_xaui_b(struct efx_nic *efx)
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{
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efx_dword_t reg;
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int count;
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EFX_POPULATE_DWORD_1(reg, XX_RST_XX_EN, 1);
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falcon_xmac_writel(efx, ®, XX_PWR_RST_REG_MAC);
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/* Give some time for the link to establish */
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for (count = 0; count < 1000; count++) { /* wait upto 10ms */
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falcon_xmac_readl(efx, ®, XX_PWR_RST_REG_MAC);
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if (EFX_DWORD_FIELD(reg, XX_RST_XX_EN) == 0) {
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falcon_setup_xaui(efx);
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return 0;
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}
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udelay(10);
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}
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EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
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return -ETIMEDOUT;
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}
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int falcon_reset_xaui(struct efx_nic *efx)
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{
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int rc;
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if (EFX_WORKAROUND_9388(efx)) {
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falcon_hold_xaui_in_rst(efx);
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efx->phy_op->reset_xaui(efx);
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rc = _falcon_reset_xaui_a(efx);
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} else {
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rc = _falcon_reset_xaui_b(efx);
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}
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return rc;
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}
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static int falcon_xgmii_status(struct efx_nic *efx)
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{
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efx_dword_t reg;
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if (FALCON_REV(efx) < FALCON_REV_B0)
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return 1;
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/* The ISR latches, so clear it and re-read */
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falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
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falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
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if (EFX_DWORD_FIELD(reg, XM_LCLFLT) ||
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EFX_DWORD_FIELD(reg, XM_RMTFLT)) {
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EFX_INFO(efx, "MGT_INT: "EFX_DWORD_FMT"\n", EFX_DWORD_VAL(reg));
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return 0;
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}
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return 1;
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}
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static void falcon_mask_status_intr(struct efx_nic *efx, int enable)
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{
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efx_dword_t reg;
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if (FALCON_REV(efx) < FALCON_REV_B0)
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return;
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/* Flush the ISR */
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if (enable)
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falcon_xmac_readl(efx, ®, XM_MGT_INT_REG_MAC_B0);
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EFX_POPULATE_DWORD_2(reg,
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XM_MSK_RMTFLT, !enable,
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XM_MSK_LCLFLT, !enable);
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falcon_xmac_writel(efx, ®, XM_MGT_INT_MSK_REG_MAC_B0);
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}
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int falcon_init_xmac(struct efx_nic *efx)
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{
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int rc;
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/* Initialize the PHY first so the clock is around */
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rc = efx->phy_op->init(efx);
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if (rc)
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goto fail1;
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rc = falcon_reset_xaui(efx);
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if (rc)
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goto fail2;
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/* Wait again. Give the PHY and MAC time to come back */
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schedule_timeout_uninterruptible(HZ / 10);
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rc = falcon_reset_xmac(efx);
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if (rc)
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goto fail2;
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falcon_mask_status_intr(efx, 1);
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return 0;
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fail2:
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efx->phy_op->fini(efx);
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fail1:
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return rc;
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}
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int falcon_xaui_link_ok(struct efx_nic *efx)
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{
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efx_dword_t reg;
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int align_done, sync_status, link_ok = 0;
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/* Read link status */
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falcon_xmac_readl(efx, ®, XX_CORE_STAT_REG_MAC);
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align_done = EFX_DWORD_FIELD(reg, XX_ALIGN_DONE);
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sync_status = EFX_DWORD_FIELD(reg, XX_SYNC_STAT);
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if (align_done && (sync_status == XX_SYNC_STAT_DECODE_SYNCED))
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link_ok = 1;
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/* Clear link status ready for next read */
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EFX_SET_DWORD_FIELD(reg, XX_COMMA_DET, XX_COMMA_DET_RESET);
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EFX_SET_DWORD_FIELD(reg, XX_CHARERR, XX_CHARERR_RESET);
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EFX_SET_DWORD_FIELD(reg, XX_DISPERR, XX_DISPERR_RESET);
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falcon_xmac_writel(efx, ®, XX_CORE_STAT_REG_MAC);
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/* If the link is up, then check the phy side of the xaui link
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* (error conditions from the wire side propoagate back through
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* the phy to the xaui side). */
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if (efx->link_up && link_ok) {
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int has_phyxs = efx->phy_op->mmds & (1 << MDIO_MMD_PHYXS);
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if (has_phyxs)
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link_ok = mdio_clause45_phyxgxs_lane_sync(efx);
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}
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/* If the PHY and XAUI links are up, then check the mac's xgmii
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* fault state */
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if (efx->link_up && link_ok)
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link_ok = falcon_xgmii_status(efx);
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return link_ok;
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}
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static void falcon_reconfigure_xmac_core(struct efx_nic *efx)
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{
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unsigned int max_frame_len;
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efx_dword_t reg;
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int rx_fc = (efx->flow_control & EFX_FC_RX) ? 1 : 0;
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/* Configure MAC - cut-thru mode is hard wired on */
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EFX_POPULATE_DWORD_3(reg,
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XM_RX_JUMBO_MODE, 1,
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XM_TX_STAT_EN, 1,
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XM_RX_STAT_EN, 1);
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falcon_xmac_writel(efx, ®, XM_GLB_CFG_REG_MAC);
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/* Configure TX */
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EFX_POPULATE_DWORD_6(reg,
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XM_TXEN, 1,
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XM_TX_PRMBL, 1,
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XM_AUTO_PAD, 1,
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XM_TXCRC, 1,
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XM_FCNTL, 1,
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XM_IPG, 0x3);
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falcon_xmac_writel(efx, ®, XM_TX_CFG_REG_MAC);
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/* Configure RX */
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EFX_POPULATE_DWORD_5(reg,
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XM_RXEN, 1,
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XM_AUTO_DEPAD, 0,
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XM_ACPT_ALL_MCAST, 1,
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XM_ACPT_ALL_UCAST, efx->promiscuous,
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XM_PASS_CRC_ERR, 1);
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falcon_xmac_writel(efx, ®, XM_RX_CFG_REG_MAC);
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/* Set frame length */
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max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
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EFX_POPULATE_DWORD_1(reg, XM_MAX_RX_FRM_SIZE, max_frame_len);
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falcon_xmac_writel(efx, ®, XM_RX_PARAM_REG_MAC);
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EFX_POPULATE_DWORD_2(reg,
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XM_MAX_TX_FRM_SIZE, max_frame_len,
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XM_TX_JUMBO_MODE, 1);
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falcon_xmac_writel(efx, ®, XM_TX_PARAM_REG_MAC);
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EFX_POPULATE_DWORD_2(reg,
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XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
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XM_DIS_FCNTL, rx_fc ? 0 : 1);
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falcon_xmac_writel(efx, ®, XM_FC_REG_MAC);
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/* Set MAC address */
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EFX_POPULATE_DWORD_4(reg,
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XM_ADR_0, efx->net_dev->dev_addr[0],
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XM_ADR_1, efx->net_dev->dev_addr[1],
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XM_ADR_2, efx->net_dev->dev_addr[2],
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XM_ADR_3, efx->net_dev->dev_addr[3]);
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falcon_xmac_writel(efx, ®, XM_ADR_LO_REG_MAC);
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EFX_POPULATE_DWORD_2(reg,
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XM_ADR_4, efx->net_dev->dev_addr[4],
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XM_ADR_5, efx->net_dev->dev_addr[5]);
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falcon_xmac_writel(efx, ®, XM_ADR_HI_REG_MAC);
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}
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/* Try and bring the Falcon side of the Falcon-Phy XAUI link fails
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* to come back up. Bash it until it comes back up */
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static int falcon_check_xaui_link_up(struct efx_nic *efx)
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{
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int max_tries, tries;
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tries = EFX_WORKAROUND_5147(efx) ? 5 : 1;
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max_tries = tries;
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if (efx->phy_type == PHY_TYPE_NONE)
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return 0;
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while (tries) {
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if (falcon_xaui_link_ok(efx))
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return 1;
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EFX_LOG(efx, "%s Clobbering XAUI (%d tries left).\n",
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__func__, tries);
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(void) falcon_reset_xaui(efx);
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udelay(200);
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tries--;
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}
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EFX_ERR(efx, "Failed to bring XAUI link back up in %d tries!\n",
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max_tries);
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return 0;
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}
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void falcon_reconfigure_xmac(struct efx_nic *efx)
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{
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int xaui_link_ok;
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falcon_mask_status_intr(efx, 0);
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falcon_deconfigure_mac_wrapper(efx);
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efx->phy_op->reconfigure(efx);
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falcon_reconfigure_xmac_core(efx);
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falcon_reconfigure_mac_wrapper(efx);
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/* Ensure XAUI link is up */
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xaui_link_ok = falcon_check_xaui_link_up(efx);
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if (xaui_link_ok && efx->link_up)
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falcon_mask_status_intr(efx, 1);
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}
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void falcon_fini_xmac(struct efx_nic *efx)
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{
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/* Isolate the MAC - PHY */
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falcon_deconfigure_mac_wrapper(efx);
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/* Potentially power down the PHY */
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efx->phy_op->fini(efx);
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}
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void falcon_update_stats_xmac(struct efx_nic *efx)
|
|
{
|
|
struct efx_mac_stats *mac_stats = &efx->mac_stats;
|
|
int rc;
|
|
|
|
rc = falcon_dma_stats(efx, XgDmaDone_offset);
|
|
if (rc)
|
|
return;
|
|
|
|
/* Update MAC stats from DMAed values */
|
|
FALCON_STAT(efx, XgRxOctets, rx_bytes);
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|
FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
|
|
FALCON_STAT(efx, XgRxPkts, rx_packets);
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|
FALCON_STAT(efx, XgRxPktsOK, rx_good);
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|
FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
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|
FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
|
|
FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
|
|
FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
|
|
FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
|
|
FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
|
|
FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
|
|
FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
|
|
FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
|
|
FALCON_STAT(efx, XgRxAlignError, rx_align_error);
|
|
FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
|
|
FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
|
|
FALCON_STAT(efx, XgRxControlPkts, rx_control);
|
|
FALCON_STAT(efx, XgRxPausePkts, rx_pause);
|
|
FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
|
|
FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
|
|
FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
|
|
FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
|
|
FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
|
|
FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
|
|
FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
|
|
FALCON_STAT(efx, XgRxLengthError, rx_length_error);
|
|
FALCON_STAT(efx, XgTxPkts, tx_packets);
|
|
FALCON_STAT(efx, XgTxOctets, tx_bytes);
|
|
FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
|
|
FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
|
|
FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
|
|
FALCON_STAT(efx, XgTxControlPkts, tx_control);
|
|
FALCON_STAT(efx, XgTxPausePkts, tx_pause);
|
|
FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
|
|
FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
|
|
FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
|
|
FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
|
|
FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
|
|
FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
|
|
FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
|
|
FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
|
|
FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
|
|
FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
|
|
FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
|
|
FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
|
|
|
|
/* Update derived statistics */
|
|
mac_stats->tx_good_bytes =
|
|
(mac_stats->tx_bytes - mac_stats->tx_bad_bytes);
|
|
mac_stats->rx_bad_bytes =
|
|
(mac_stats->rx_bytes - mac_stats->rx_good_bytes);
|
|
}
|
|
|
|
#define EFX_XAUI_RETRAIN_MAX 8
|
|
|
|
int falcon_check_xmac(struct efx_nic *efx)
|
|
{
|
|
unsigned xaui_link_ok;
|
|
int rc;
|
|
|
|
falcon_mask_status_intr(efx, 0);
|
|
xaui_link_ok = falcon_xaui_link_ok(efx);
|
|
|
|
if (EFX_WORKAROUND_5147(efx) && !xaui_link_ok)
|
|
(void) falcon_reset_xaui(efx);
|
|
|
|
/* Call the PHY check_hw routine */
|
|
rc = efx->phy_op->check_hw(efx);
|
|
|
|
/* Unmask interrupt if everything was (and still is) ok */
|
|
if (xaui_link_ok && efx->link_up)
|
|
falcon_mask_status_intr(efx, 1);
|
|
|
|
return rc;
|
|
}
|
|
|
|
/* Simulate a PHY event */
|
|
void falcon_xmac_sim_phy_event(struct efx_nic *efx)
|
|
{
|
|
efx_qword_t phy_event;
|
|
|
|
EFX_POPULATE_QWORD_2(phy_event,
|
|
EV_CODE, GLOBAL_EV_DECODE,
|
|
XG_PHY_INTR, 1);
|
|
falcon_generate_event(&efx->channel[0], &phy_event);
|
|
}
|
|
|
|
int falcon_xmac_get_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
|
{
|
|
mdio_clause45_get_settings(efx, ecmd);
|
|
ecmd->transceiver = XCVR_INTERNAL;
|
|
ecmd->phy_address = efx->mii.phy_id;
|
|
ecmd->autoneg = AUTONEG_DISABLE;
|
|
ecmd->duplex = DUPLEX_FULL;
|
|
return 0;
|
|
}
|
|
|
|
int falcon_xmac_set_settings(struct efx_nic *efx, struct ethtool_cmd *ecmd)
|
|
{
|
|
if (ecmd->transceiver != XCVR_INTERNAL)
|
|
return -EINVAL;
|
|
if (ecmd->autoneg != AUTONEG_DISABLE)
|
|
return -EINVAL;
|
|
if (ecmd->duplex != DUPLEX_FULL)
|
|
return -EINVAL;
|
|
|
|
return mdio_clause45_set_settings(efx, ecmd);
|
|
}
|
|
|
|
|
|
int falcon_xmac_set_pause(struct efx_nic *efx, enum efx_fc_type flow_control)
|
|
{
|
|
int reset;
|
|
|
|
if (flow_control & EFX_FC_AUTO) {
|
|
EFX_LOG(efx, "10G does not support flow control "
|
|
"autonegotiation\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if ((flow_control & EFX_FC_TX) && !(flow_control & EFX_FC_RX))
|
|
return -EINVAL;
|
|
|
|
/* TX flow control may automatically turn itself off if the
|
|
* link partner (intermittently) stops responding to pause
|
|
* frames. There isn't any indication that this has happened,
|
|
* so the best we do is leave it up to the user to spot this
|
|
* and fix it be cycling transmit flow control on this end. */
|
|
reset = ((flow_control & EFX_FC_TX) &&
|
|
!(efx->flow_control & EFX_FC_TX));
|
|
if (EFX_WORKAROUND_11482(efx) && reset) {
|
|
if (FALCON_REV(efx) >= FALCON_REV_B0) {
|
|
/* Recover by resetting the EM block */
|
|
if (efx->link_up)
|
|
falcon_drain_tx_fifo(efx);
|
|
} else {
|
|
/* Schedule a reset to recover */
|
|
efx_schedule_reset(efx, RESET_TYPE_INVISIBLE);
|
|
}
|
|
}
|
|
|
|
efx->flow_control = flow_control;
|
|
|
|
return 0;
|
|
}
|