kernel-ark/include/asm-mips
Ingo Molnar fb1c8f93d8 [PATCH] spinlock consolidation
This patch (written by me and also containing many suggestions of Arjan van
de Ven) does a major cleanup of the spinlock code.  It does the following
things:

 - consolidates and enhances the spinlock/rwlock debugging code

 - simplifies the asm/spinlock.h files

 - encapsulates the raw spinlock type and moves generic spinlock
   features (such as ->break_lock) into the generic code.

 - cleans up the spinlock code hierarchy to get rid of the spaghetti.

Most notably there's now only a single variant of the debugging code,
located in lib/spinlock_debug.c.  (previously we had one SMP debugging
variant per architecture, plus a separate generic one for UP builds)

Also, i've enhanced the rwlock debugging facility, it will now track
write-owners.  There is new spinlock-owner/CPU-tracking on SMP builds too.
All locks have lockup detection now, which will work for both soft and hard
spin/rwlock lockups.

The arch-level include files now only contain the minimally necessary
subset of the spinlock code - all the rest that can be generalized now
lives in the generic headers:

 include/asm-i386/spinlock_types.h       |   16
 include/asm-x86_64/spinlock_types.h     |   16

I have also split up the various spinlock variants into separate files,
making it easier to see which does what. The new layout is:

   SMP                         |  UP
   ----------------------------|-----------------------------------
   asm/spinlock_types_smp.h    |  linux/spinlock_types_up.h
   linux/spinlock_types.h      |  linux/spinlock_types.h
   asm/spinlock_smp.h          |  linux/spinlock_up.h
   linux/spinlock_api_smp.h    |  linux/spinlock_api_up.h
   linux/spinlock.h            |  linux/spinlock.h

/*
 * here's the role of the various spinlock/rwlock related include files:
 *
 * on SMP builds:
 *
 *  asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the
 *                        initializers
 *
 *  linux/spinlock_types.h:
 *                        defines the generic type and initializers
 *
 *  asm/spinlock.h:       contains the __raw_spin_*()/etc. lowlevel
 *                        implementations, mostly inline assembly code
 *
 *   (also included on UP-debug builds:)
 *
 *  linux/spinlock_api_smp.h:
 *                        contains the prototypes for the _spin_*() APIs.
 *
 *  linux/spinlock.h:     builds the final spin_*() APIs.
 *
 * on UP builds:
 *
 *  linux/spinlock_type_up.h:
 *                        contains the generic, simplified UP spinlock type.
 *                        (which is an empty structure on non-debug builds)
 *
 *  linux/spinlock_types.h:
 *                        defines the generic type and initializers
 *
 *  linux/spinlock_up.h:
 *                        contains the __raw_spin_*()/etc. version of UP
 *                        builds. (which are NOPs on non-debug, non-preempt
 *                        builds)
 *
 *   (included on UP-non-debug builds:)
 *
 *  linux/spinlock_api_up.h:
 *                        builds the _spin_*() APIs.
 *
 *  linux/spinlock.h:     builds the final spin_*() APIs.
 */

All SMP and UP architectures are converted by this patch.

arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via
crosscompilers.  m32r, mips, sh, sparc, have not been tested yet, but should
be mostly fine.

From: Grant Grundler <grundler@parisc-linux.org>

  Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU).
  Builds 32-bit SMP kernel (not booted or tested).  I did not try to build
  non-SMP kernels.  That should be trivial to fix up later if necessary.

  I converted bit ops atomic_hash lock to raw_spinlock_t.  Doing so avoids
  some ugly nesting of linux/*.h and asm/*.h files.  Those particular locks
  are well tested and contained entirely inside arch specific code.  I do NOT
  expect any new issues to arise with them.

 If someone does ever need to use debug/metrics with them, then they will
  need to unravel this hairball between spinlocks, atomic ops, and bit ops
  that exist only because parisc has exactly one atomic instruction: LDCW
  (load and clear word).

From: "Luck, Tony" <tony.luck@intel.com>

   ia64 fix

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Arjan van de Ven <arjanv@infradead.org>
Signed-off-by: Grant Grundler <grundler@parisc-linux.org>
Cc: Matthew Wilcox <willy@debian.org>
Signed-off-by: Hirokazu Takata <takata@linux-m32r.org>
Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-09-10 10:06:21 -07:00
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8253pit.h
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addrspace.h
asm.h
asmmacro-32.h
asmmacro-64.h
asmmacro.h
atomic.h
auxvec.h
bcache.h
bitops.h
bootinfo.h
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break.h
bug.h
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fpu_emulator.h
fpu.h
futex.h
gdb-stub.h
gfx.h
gt64120.h
gt64240.h
hardirq.h
hazards.h
highmem.h
hw_irq.h
i8259.h
ide.h
inst.h
interrupt.h
inventory.h
io.h
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ioctls.h
ipc.h
ipcbuf.h
irq_cpu.h
irq.h
isadep.h
it8712.h
jazz.h
jazzdma.h
kmap_types.h
linkage.h
local.h
m48t35.h
m48t37.h
marvell.h
mc146818-time.h
mc146818rtc.h
mipsprom.h
mipsregs.h
mman.h
mmu_context.h
mmu.h
mmzone.h
module.h
msc01_ic.h
msgbuf.h
namei.h
nile4.h
numnodes.h
paccess.h
page.h
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parport.h
pci.h
percpu.h
pgalloc.h
pgtable-32.h
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pgtable-bits.h
pgtable.h
pmon.h
poll.h
posix_types.h
prctl.h
prefetch.h
processor.h
ptrace.h
qemu.h
r4kcache.h
reboot.h
reg.h
regdef.h
resource.h
riscos-syscall.h
rtc.h
scatterlist.h
sections.h
segment.h
semaphore.h
sembuf.h
serial.h
setup.h
sgialib.h
sgiarcs.h
sgidefs.h
shmbuf.h
shmparam.h
sigcontext.h
siginfo.h
signal.h
sim.h
smp.h
sni.h
socket.h
sockios.h
spinlock_types.h
spinlock.h
stackframe.h
stat.h
statfs.h
string.h
suspend.h
sysmips.h
system.h
termbits.h
termios.h
thread_info.h
time.h
timex.h
titan_dep.h
tlb.h
tlbdebug.h
tlbflush.h
topology.h
traps.h
tx3912.h
types.h
uaccess.h
ucontext.h
unaligned.h
unistd.h
user.h
vga.h
war.h
watch.h
wbflush.h
xor.h
xxs1500.h