35832e26f9
Patch to add core platform support for the PMC-Sierra MSP71xx devices. Signed-off-by: Marc St-Jean <Marc_St-Jean@pmc-sierra.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
237 lines
6.4 KiB
C
237 lines
6.4 KiB
C
/*
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* SMP/VPE-safe functions to access "registers" (see note).
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*
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* NOTES:
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* - These macros use ll/sc instructions, so it is your responsibility to
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* ensure these are available on your platform before including this file.
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* - The MIPS32 spec states that ll/sc results are undefined for uncached
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* accesses. This means they can't be used on HW registers accessed
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* through kseg1. Code which requires these macros for this purpose must
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* front-end the registers with cached memory "registers" and have a single
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* thread update the actual HW registers.
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* - A maximum of 2k of code can be inserted between ll and sc. Every
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* memory accesses between the instructions will increase the chance of
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* sc failing and having to loop.
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* - When using custom_read_reg32/custom_write_reg32 only perform the
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* necessary logical operations on the register value in between these
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* two calls. All other logic should be performed before the first call.
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* - There is a bug on the R10000 chips which has a workaround. If you
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* are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
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* to be non-zero. If you are using this header from within linux, you may
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* include <asm/war.h> before including this file to have this defined
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* appropriately for you.
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*
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* Copyright 2005-2007 PMC-Sierra, Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
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* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc., 675
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* Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef __ASM_REGOPS_H__
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#define __ASM_REGOPS_H__
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#include <linux/types.h>
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#include <asm/war.h>
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#ifndef R10000_LLSC_WAR
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#define R10000_LLSC_WAR 0
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#endif
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#if R10000_LLSC_WAR == 1
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#define __beqz "beqzl "
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#else
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#define __beqz "beqz "
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#endif
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#ifndef _LINUX_TYPES_H
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typedef unsigned int u32;
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#endif
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/*
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* Sets all the masked bits to the corresponding value bits
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*/
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static inline void set_value_reg32(volatile u32 *const addr,
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u32 const mask,
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u32 const value)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set mips3 \n"
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"1: ll %0, %1 # set_value_reg32 \n"
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" and %0, %2 \n"
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" or %0, %3 \n"
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" sc %0, %1 \n"
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" "__beqz"%0, 1b \n"
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" nop \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*addr)
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: "ir" (~mask), "ir" (value), "m" (*addr));
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}
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/*
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* Sets all the masked bits to '1'
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*/
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static inline void set_reg32(volatile u32 *const addr,
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u32 const mask)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set mips3 \n"
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"1: ll %0, %1 # set_reg32 \n"
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" or %0, %2 \n"
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" sc %0, %1 \n"
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" "__beqz"%0, 1b \n"
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" nop \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*addr)
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: "ir" (mask), "m" (*addr));
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}
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/*
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* Sets all the masked bits to '0'
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*/
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static inline void clear_reg32(volatile u32 *const addr,
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u32 const mask)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set mips3 \n"
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"1: ll %0, %1 # clear_reg32 \n"
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" and %0, %2 \n"
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" sc %0, %1 \n"
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" "__beqz"%0, 1b \n"
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" nop \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*addr)
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: "ir" (~mask), "m" (*addr));
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}
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/*
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* Toggles all masked bits from '0' to '1' and '1' to '0'
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*/
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static inline void toggle_reg32(volatile u32 *const addr,
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u32 const mask)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set mips3 \n"
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"1: ll %0, %1 # toggle_reg32 \n"
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" xor %0, %2 \n"
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" sc %0, %1 \n"
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" "__beqz"%0, 1b \n"
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" nop \n"
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" .set pop \n"
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: "=&r" (temp), "=m" (*addr)
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: "ir" (mask), "m" (*addr));
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}
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/*
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* Read all masked bits others are returned as '0'
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*/
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static inline u32 read_reg32(volatile u32 *const addr,
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u32 const mask)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" lw %0, %1 # read \n"
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" and %0, %2 # mask \n"
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" .set pop \n"
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: "=&r" (temp)
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: "m" (*addr), "ir" (mask));
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return temp;
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}
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/*
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* blocking_read_reg32 - Read address with blocking load
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*
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* Uncached writes need to be read back to ensure they reach RAM.
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* The returned value must be 'used' to prevent from becoming a
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* non-blocking load.
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*/
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static inline u32 blocking_read_reg32(volatile u32 *const addr)
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{
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u32 temp;
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__asm__ __volatile__(
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" .set push \n"
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" .set noreorder \n"
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" lw %0, %1 # read \n"
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" move %0, %0 # block \n"
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" .set pop \n"
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: "=&r" (temp)
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: "m" (*addr));
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return temp;
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}
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/*
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* For special strange cases only:
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*
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* If you need custom processing within a ll/sc loop, use the following macros
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* VERY CAREFULLY:
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*
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* u32 tmp; <-- Define a variable to hold the data
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*
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* custom_read_reg32(address, tmp); <-- Reads the address and put the value
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* in the 'tmp' variable given
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*
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* From here on out, you are (basicly) atomic, so don't do anything too
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* fancy!
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* Also, this code may loop if the end of this block fails to write
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* everything back safely due do the other CPU, so do NOT do anything
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* with side-effects!
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*
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* custom_write_reg32(address, tmp); <-- Writes back 'tmp' safely.
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*/
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#define custom_read_reg32(address, tmp) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set mips3 \n" \
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"1: ll %0, %1 #custom_read_reg32 \n" \
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" .set pop \n" \
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: "=r" (tmp), "=m" (*address) \
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: "m" (*address))
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#define custom_write_reg32(address, tmp) \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set mips3 \n" \
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" sc %0, %1 #custom_write_reg32 \n" \
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" "__beqz"%0, 1b \n" \
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" nop \n" \
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" .set pop \n" \
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: "=&r" (tmp), "=m" (*address) \
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: "0" (tmp), "m" (*address))
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#endif /* __ASM_REGOPS_H__ */
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