Jingoo Han 8affaf5c76 video: exynos_dp: add analog and pll control setting ... This patch adds analog and pll control setting. This control setting is used for DP TX PHY block to set the values as below. It is beneficial to improve analog characteristics. - TX terminal registor is 50 Ohm. - Reference clock of PHY is 24 MHz. - Power source for TX digital logic is 1.0625 V. - Power source for internal clock driver is 1.0625 V. - PLL VCO range setting is 600 uA. - Power down ring osc is turned off. - AUX terminal resistor is 50 Ohm. - AUX channel current is 8 mA and multiplied by 2. - TX channel output amplitude is 400 mV. Signed-off-by: Jingoo Han <jg1.han@samsung.com> Signed-off-by: Florian Tobias Schandinat <FlorianSchandinat@gmx.de>		2012-04-16 04:19:00 +00:00
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exynos_dp_core.c	video: exynos_dp: replace char pointer with char array for adjust_request variable	2012-04-16 04:18:38 +00:00
exynos_dp_core.h	video: exynos_dp: add analog and pll control setting	2012-04-16 04:19:00 +00:00
exynos_dp_reg.c	video: exynos_dp: add analog and pll control setting	2012-04-16 04:19:00 +00:00
exynos_dp_reg.h	video: exynos_dp: add analog and pll control setting	2012-04-16 04:19:00 +00:00
exynos_mipi_dsi_common.c
exynos_mipi_dsi_common.h
exynos_mipi_dsi_lowlevel.c
exynos_mipi_dsi_lowlevel.h
exynos_mipi_dsi_regs.h
exynos_mipi_dsi.c
Kconfig	video: support DP controller driver	2012-02-13 03:02:30 +00:00
Makefile	video: support DP controller driver	2012-02-13 03:02:30 +00:00
s6e8ax0.c
s6e8ax0.h