5f53d8ca3d
Driver from Realtek for the Realtek RTL8192 USB wifi device Based on the r8187 driver from Andrea Merello <andreamrl@tiscali.it> and others. Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
139 lines
4.6 KiB
C
139 lines
4.6 KiB
C
/*****************************************************************************
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* Copyright(c) 2008, RealTEK Technology Inc. All Right Reserved.
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*
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* Module: __INC_HAL8192SPHYCFG_H
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*
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*
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* Note:
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*
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*
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* Export: Constants, macro, functions(API), global variables(None).
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*
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* Abbrev:
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*
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* History:
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* Data Who Remark
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* 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
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* 2. Reorganize code architecture.
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*
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*****************************************************************************/
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/* Check to see if the file has been included already. */
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#ifndef _R8192S_PHY_H
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#define _R8192S_PHY_H
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/*--------------------------Define Parameters-------------------------------*/
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#define LOOP_LIMIT 5
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#define MAX_STALL_TIME 50 //us
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#define AntennaDiversityValue 0x80 //(dev->bSoftwareAntennaDiversity ? 0x00:0x80)
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#define MAX_TXPWR_IDX_NMODE_92S 63
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//#define delay_ms(_t) PlatformStallExecution(1000*(_t))
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//#define delay_us(_t) PlatformStallExecution(_t)
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/* Channel switch:The size of command tables for switch channel*/
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#define MAX_PRECMD_CNT 16
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#define MAX_RFDEPENDCMD_CNT 16
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#define MAX_POSTCMD_CNT 16
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/*------------------------------Define structure----------------------------*/
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typedef enum _SwChnlCmdID{
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CmdID_End,
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CmdID_SetTxPowerLevel,
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CmdID_BBRegWrite10,
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CmdID_WritePortUlong,
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CmdID_WritePortUshort,
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CmdID_WritePortUchar,
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CmdID_RF_WriteReg,
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}SwChnlCmdID;
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/* 1. Switch channel related */
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typedef struct _SwChnlCmd{
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SwChnlCmdID CmdID;
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u32 Para1;
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u32 Para2;
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u32 msDelay;
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}__attribute__ ((packed)) SwChnlCmd;
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extern u32 rtl819XMACPHY_Array_PG[];
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extern u32 rtl819XPHY_REG_1T2RArray[];
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extern u32 rtl819XAGCTAB_Array[];
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extern u32 rtl819XRadioA_Array[];
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extern u32 rtl819XRadioB_Array[];
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extern u32 rtl819XRadioC_Array[];
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extern u32 rtl819XRadioD_Array[];
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typedef enum _HW90_BLOCK{
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HW90_BLOCK_MAC = 0,
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HW90_BLOCK_PHY0 = 1,
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HW90_BLOCK_PHY1 = 2,
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HW90_BLOCK_RF = 3,
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HW90_BLOCK_MAXIMUM = 4, // Never use this
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}HW90_BLOCK_E, *PHW90_BLOCK_E;
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typedef enum _RF90_RADIO_PATH{
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RF90_PATH_A = 0, //Radio Path A
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RF90_PATH_B = 1, //Radio Path B
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RF90_PATH_C = 2, //Radio Path C
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RF90_PATH_D = 3, //Radio Path D
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RF90_PATH_MAX = 4, //Max RF number 90 support
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}RF90_RADIO_PATH_E, *PRF90_RADIO_PATH_E;
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#define bMaskByte0 0xff
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#define bMaskByte1 0xff00
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#define bMaskByte2 0xff0000
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#define bMaskByte3 0xff000000
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#define bMaskHWord 0xffff0000
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#define bMaskLWord 0x0000ffff
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#define bMaskDWord 0xffffffff
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typedef enum _VERSION_8190{
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// RTL8190
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VERSION_8190_BD=0x3,
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VERSION_8190_BE
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}VERSION_8190,*PVERSION_8190;
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//
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// BB and RF register read/write
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//
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extern u32 rtl8192_QueryBBReg(struct net_device* dev,u32 RegAddr, u32 BitMask);
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extern void rtl8192_setBBreg(struct net_device* dev,u32 RegAddr, u32 BitMask,u32 Data);
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extern u32 rtl8192_phy_QueryRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr, u32 BitMask);
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extern void rtl8192_phy_SetRFReg(struct net_device* dev,RF90_RADIO_PATH_E eRFPath, u32 RegAddr,u32 BitMask,u32 Data);
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bool rtl8192_phy_checkBBAndRF(struct net_device* dev, HW90_BLOCK_E CheckBlock, RF90_RADIO_PATH_E eRFPath);
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/* MAC/BB/RF HAL config */
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extern bool PHY_MACConfig8192S(struct net_device* dev);
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extern bool PHY_BBConfig8192S(struct net_device* dev);
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extern bool PHY_RFConfig8192S(struct net_device* dev);
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extern u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device* dev,RF90_RADIO_PATH_E eRFPath);
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extern void rtl8192_SetBWMode(struct net_device* dev,HT_CHANNEL_WIDTH ChnlWidth,HT_EXTCHNL_OFFSET Offset );
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extern u8 rtl8192_phy_SwChnl(struct net_device* dev,u8 channel);
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extern u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device* dev,u32 eRFPath );
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extern void rtl8192_BBConfig(struct net_device* dev);
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extern void PHY_IQCalibrateBcut(struct net_device* dev);
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extern void PHY_IQCalibrate(struct net_device* dev);
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extern void PHY_GetHWRegOriginalValue(struct net_device* dev);
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#if (LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,20))
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extern void InitialGainOperateWorkItemCallBack(struct work_struct *work);
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#else
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extern void InitialGainOperateWorkItemCallBack(struct net_device *dev);
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#endif
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void PHY_SetTxPowerLevel8192S(struct net_device* dev, u8 channel);
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void PHY_InitialGain8192S(struct net_device* dev,u8 Operation );
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/*--------------------------Exported Function prototype---------------------*/
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bool HalSetFwCmd8192S(struct net_device* dev, FW_CMD_IO_TYPE FwCmdIO);
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extern void PHY_SetBeaconHwReg( struct net_device* dev, u16 BeaconInterval);
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void ChkFwCmdIoDone(struct net_device* dev);
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#endif // __INC_HAL8192SPHYCFG_H
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