e7eda91f63
this moves to generic IP module reset framework, and make other drivers use common device_reset() API. Cc: Srinivas Kandagatla <srinivas.kandagatla@st.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Bin Shi <Bin.Shi@csr.com> Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
43 lines
1.3 KiB
Plaintext
43 lines
1.3 KiB
Plaintext
CSR SiRFSoC Reset Controller
|
|
======================================
|
|
|
|
Please also refer to reset.txt in this directory for common reset
|
|
controller binding usage.
|
|
|
|
Required properties:
|
|
- compatible: Should be "sirf,prima2-rstc" or "sirf,marco-rstc"
|
|
- reg: should be register base and length as documented in the
|
|
datasheet
|
|
- #reset-cells: 1, see below
|
|
|
|
example:
|
|
|
|
rstc: reset-controller@88010000 {
|
|
compatible = "sirf,prima2-rstc";
|
|
reg = <0x88010000 0x1000>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
Specifying reset lines connected to IP modules
|
|
==============================================
|
|
|
|
The reset controller(rstc) manages various reset sources. This module provides
|
|
reset signals for most blocks in system. Those device nodes should specify the
|
|
reset line on the rstc in their resets property, containing a phandle to the
|
|
rstc device node and a RESET_INDEX specifying which module to reset, as described
|
|
in reset.txt.
|
|
|
|
For SiRFSoC, RESET_INDEX is just reset_bit defined in SW_RST0 and SW_RST1 registers.
|
|
For modules whose rest_bit is in SW_RST0, its RESET_INDEX is 0~31. For modules whose
|
|
rest_bit is in SW_RST1, its RESET_INDEX is 32~63.
|
|
|
|
example:
|
|
|
|
vpp@90020000 {
|
|
compatible = "sirf,prima2-vpp";
|
|
reg = <0x90020000 0x10000>;
|
|
interrupts = <31>;
|
|
clocks = <&clks 35>;
|
|
resets = <&rstc 6>;
|
|
};
|