8bd137d4c0
This commit adds documentation for the devicetree bindings of the pinctrl-ingenic driver, which handles pin configuration and pin muxing of the Ingenic SoCs currently supported by the Linux kernel. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
42 lines
1.3 KiB
Plaintext
42 lines
1.3 KiB
Plaintext
Ingenic jz47xx pin controller
|
|
|
|
Please refer to pinctrl-bindings.txt in this directory for details of the
|
|
common pinctrl bindings used by client devices, including the meaning of the
|
|
phrase "pin configuration node".
|
|
|
|
For the jz47xx SoCs, pin control is tightly bound with GPIO ports. All pins may
|
|
be used as GPIOs, multiplexed device functions are configured within the
|
|
GPIO port configuration registers and it is typical to refer to pins using the
|
|
naming scheme "PxN" where x is a character identifying the GPIO port with
|
|
which the pin is associated and N is an integer from 0 to 31 identifying the
|
|
pin within that GPIO port. For example PA0 is the first pin in GPIO port A, and
|
|
PB31 is the last pin in GPIO port B. The jz4740 contains 4 GPIO ports, PA to
|
|
PD, for a total of 128 pins. The jz4780 contains 6 GPIO ports, PA to PF, for a
|
|
total of 192 pins.
|
|
|
|
|
|
Required properties:
|
|
--------------------
|
|
|
|
- compatible: One of:
|
|
- "ingenic,jz4740-pinctrl"
|
|
- "ingenic,jz4770-pinctrl"
|
|
- "ingenic,jz4780-pinctrl"
|
|
- reg: Address range of the pinctrl registers.
|
|
|
|
|
|
GPIO sub-nodes
|
|
--------------
|
|
|
|
The pinctrl node can have optional sub-nodes for the Ingenic GPIO driver;
|
|
please refer to ../gpio/ingenic,gpio.txt.
|
|
|
|
|
|
Example:
|
|
--------
|
|
|
|
pinctrl: pin-controller@10010000 {
|
|
compatible = "ingenic,jz4740-pinctrl";
|
|
reg = <0x10010000 0x400>;
|
|
};
|