a0e60b2033
Here's a revised version. This re-introduces the set_bits() function from ppc64, which I removed because I thought it was unused (it exists on no other arch). In fact it is used in the powermac interrupt code (but not on pSeries). - We use LARXL/STCXL macros to generate the right (32 or 64 bit) instructions, similar to LDL/STL from ppc_asm.h, used in fpu.S - ppc32 previously used a full "sync" barrier at the end of test_and_*_bit(), whereas ppc64 used an "isync". The merged version uses "isync", since I believe that's sufficient. - The ppc64 versions of then minix_*() bitmap functions have changed semantics. Previously on ppc64, these functions were big-endian (that is bit 0 was the LSB in the first 64-bit, big-endian word). On ppc32 (and x86, for that matter, they were little-endian. As far as I can tell, the big-endian usage was simply wrong - I guess no-one ever tried to use minixfs on ppc64. - On ppc32 find_next_bit() and find_next_zero_bit() are no longer inline (they were already out-of-line on ppc64). - For ppc64, sched_find_first_bit() has moved from mmu_context.h to the merged bitops. What it was doing in mmu_context.h in the first place, I have no idea. - The fls() function is now implemented using the cntlzw instruction on ppc64, instead of generic_fls(), as it already was on ppc32. - For ARCH=ppc, this patch requires adding arch/powerpc/lib to the arch/ppc/Makefile. This in turn requires some changes to arch/powerpc/lib/Makefile which didn't correctly handle ARCH=ppc. Built and running on G5. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@samba.org>
438 lines
12 KiB
C
438 lines
12 KiB
C
/*
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* PowerPC atomic bit operations.
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*
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* Merged version by David Gibson <david@gibson.dropbear.id.au>.
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* Based on ppc64 versions by: Dave Engebretsen, Todd Inglett, Don
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* Reed, Pat McCarthy, Peter Bergner, Anton Blanchard. They
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* originally took it from the ppc32 code.
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*
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* Within a word, bits are numbered LSB first. Lot's of places make
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* this assumption by directly testing bits with (val & (1<<nr)).
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* This can cause confusion for large (> 1 word) bitmaps on a
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* big-endian system because, unlike little endian, the number of each
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* bit depends on the word size.
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*
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* The bitop functions are defined to work on unsigned longs, so for a
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* ppc64 system the bits end up numbered:
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* |63..............0|127............64|191...........128|255...........196|
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* and on ppc32:
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* |31.....0|63....31|95....64|127...96|159..128|191..160|223..192|255..224|
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*
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* There are a few little-endian macros used mostly for filesystem
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* bitmaps, these work on similar bit arrays layouts, but
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* byte-oriented:
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* |7...0|15...8|23...16|31...24|39...32|47...40|55...48|63...56|
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*
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* The main difference is that bit 3-5 (64b) or 3-4 (32b) in the bit
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* number field needs to be reversed compared to the big-endian bit
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* fields. This can be achieved by XOR with 0x38 (64b) or 0x18 (32b).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#ifndef _ASM_POWERPC_BITOPS_H
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#define _ASM_POWERPC_BITOPS_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <asm/atomic.h>
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#include <asm/synch.h>
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/*
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* clear_bit doesn't imply a memory barrier
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*/
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#define smp_mb__before_clear_bit() smp_mb()
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#define smp_mb__after_clear_bit() smp_mb()
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#define BITOP_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
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#define BITOP_WORD(nr) ((nr) / BITS_PER_LONG)
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#define BITOP_LE_SWIZZLE ((BITS_PER_LONG-1) & ~0x7)
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#ifdef CONFIG_PPC64
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#define LARXL "ldarx"
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#define STCXL "stdcx."
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#define CNTLZL "cntlzd"
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#else
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#define LARXL "lwarx"
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#define STCXL "stwcx."
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#define CNTLZL "cntlzw"
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#endif
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static __inline__ void set_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long old;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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"1:" LARXL " %0,0,%3 # set_bit\n"
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"or %0,%0,%2\n"
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PPC405_ERR77(0,%3)
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STCXL " %0,0,%3\n"
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"bne- 1b"
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: "=&r"(old), "=m"(*p)
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: "r"(mask), "r"(p), "m"(*p)
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: "cc" );
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}
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static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long old;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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"1:" LARXL " %0,0,%3 # set_bit\n"
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"andc %0,%0,%2\n"
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PPC405_ERR77(0,%3)
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STCXL " %0,0,%3\n"
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"bne- 1b"
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: "=&r"(old), "=m"(*p)
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: "r"(mask), "r"(p), "m"(*p)
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: "cc" );
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}
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static __inline__ void change_bit(int nr, volatile unsigned long *addr)
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{
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unsigned long old;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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"1:" LARXL " %0,0,%3 # set_bit\n"
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"xor %0,%0,%2\n"
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PPC405_ERR77(0,%3)
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STCXL " %0,0,%3\n"
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"bne- 1b"
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: "=&r"(old), "=m"(*p)
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: "r"(mask), "r"(p), "m"(*p)
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: "cc" );
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}
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static __inline__ int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long old, t;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1:" LARXL " %0,0,%3 # test_and_set_bit\n"
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"or %1,%0,%2 \n"
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PPC405_ERR77(0,%3)
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STCXL " %1,0,%3 \n"
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"bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (old), "=&r" (t)
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: "r" (mask), "r" (p)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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static __inline__ int test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long old, t;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1:" LARXL " %0,0,%3 # test_and_clear_bit\n"
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"andc %1,%0,%2 \n"
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PPC405_ERR77(0,%3)
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STCXL " %1,0,%3 \n"
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"bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (old), "=&r" (t)
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: "r" (mask), "r" (p)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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static __inline__ int test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long old, t;
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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__asm__ __volatile__(
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EIEIO_ON_SMP
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"1:" LARXL " %0,0,%3 # test_and_change_bit\n"
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"xor %1,%0,%2 \n"
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PPC405_ERR77(0,%3)
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STCXL " %1,0,%3 \n"
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"bne- 1b"
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ISYNC_ON_SMP
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: "=&r" (old), "=&r" (t)
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: "r" (mask), "r" (p)
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: "cc", "memory");
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return (old & mask) != 0;
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}
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static __inline__ void set_bits(unsigned long mask, unsigned long *addr)
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{
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unsigned long old;
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__asm__ __volatile__(
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"1:" LARXL " %0,0,%3 # set_bit\n"
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"or %0,%0,%2\n"
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STCXL " %0,0,%3\n"
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"bne- 1b"
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: "=&r" (old), "=m" (*addr)
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: "r" (mask), "r" (addr), "m" (*addr)
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: "cc");
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}
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/* Non-atomic versions */
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static __inline__ int test_bit(unsigned long nr,
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__const__ volatile unsigned long *addr)
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{
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return 1UL & (addr[BITOP_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
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}
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static __inline__ void __set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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*p |= mask;
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}
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static __inline__ void __clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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*p &= ~mask;
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}
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static __inline__ void __change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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*p ^= mask;
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}
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static __inline__ int __test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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unsigned long old = *p;
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*p = old | mask;
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return (old & mask) != 0;
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}
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static __inline__ int __test_and_clear_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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unsigned long old = *p;
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*p = old & ~mask;
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return (old & mask) != 0;
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}
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static __inline__ int __test_and_change_bit(unsigned long nr,
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volatile unsigned long *addr)
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{
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unsigned long mask = BITOP_MASK(nr);
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unsigned long *p = ((unsigned long *)addr) + BITOP_WORD(nr);
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unsigned long old = *p;
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*p = old ^ mask;
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return (old & mask) != 0;
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}
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/*
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* Return the zero-based bit position (LE, not IBM bit numbering) of
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* the most significant 1-bit in a double word.
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*/
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static __inline__ int __ilog2(unsigned long x)
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{
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int lz;
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asm (CNTLZL " %0,%1" : "=r" (lz) : "r" (x));
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return BITS_PER_LONG - 1 - lz;
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}
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/*
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* Determines the bit position of the least significant 0 bit in the
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* specified double word. The returned bit position will be
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* zero-based, starting from the right side (63/31 - 0).
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*/
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static __inline__ unsigned long ffz(unsigned long x)
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{
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/* no zero exists anywhere in the 8 byte area. */
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if ((x = ~x) == 0)
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return BITS_PER_LONG;
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/*
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* Calculate the bit position of the least signficant '1' bit in x
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* (since x has been changed this will actually be the least signficant
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* '0' bit in * the original x). Note: (x & -x) gives us a mask that
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* is the least significant * (RIGHT-most) 1-bit of the value in x.
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*/
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return __ilog2(x & -x);
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}
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static __inline__ int __ffs(unsigned long x)
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{
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return __ilog2(x & -x);
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}
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/*
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* ffs: find first bit set. This is defined the same way as
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* the libc and compiler builtin ffs routines, therefore
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* differs in spirit from the above ffz (man ffs).
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*/
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static __inline__ int ffs(int x)
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{
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unsigned long i = (unsigned long)x;
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return __ilog2(i & -i) + 1;
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}
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/*
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* fls: find last (most-significant) bit set.
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* Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
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*/
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static __inline__ int fls(unsigned int x)
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{
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int lz;
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asm ("cntlzw %0,%1" : "=r" (lz) : "r" (x));
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return 32 - lz;
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}
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/*
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* hweightN: returns the hamming weight (i.e. the number
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* of bits set) of a N-bit word
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*/
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#define hweight64(x) generic_hweight64(x)
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#define hweight32(x) generic_hweight32(x)
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#define hweight16(x) generic_hweight16(x)
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#define hweight8(x) generic_hweight8(x)
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#define find_first_zero_bit(addr, size) find_next_zero_bit((addr), (size), 0)
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unsigned long find_next_zero_bit(const unsigned long *addr,
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unsigned long size, unsigned long offset);
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/**
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* find_first_bit - find the first set bit in a memory region
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* @addr: The address to start the search at
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* @size: The maximum size to search
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*
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* Returns the bit-number of the first set bit, not the number of the byte
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* containing a bit.
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*/
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#define find_first_bit(addr, size) find_next_bit((addr), (size), 0)
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unsigned long find_next_bit(const unsigned long *addr,
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unsigned long size, unsigned long offset);
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/* Little-endian versions */
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static __inline__ int test_le_bit(unsigned long nr,
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__const__ unsigned long *addr)
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{
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__const__ unsigned char *tmp = (__const__ unsigned char *) addr;
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return (tmp[nr >> 3] >> (nr & 7)) & 1;
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}
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#define __set_le_bit(nr, addr) \
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__set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define __clear_le_bit(nr, addr) \
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__clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define test_and_set_le_bit(nr, addr) \
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test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define test_and_clear_le_bit(nr, addr) \
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test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define __test_and_set_le_bit(nr, addr) \
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__test_and_set_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define __test_and_clear_le_bit(nr, addr) \
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__test_and_clear_bit((nr) ^ BITOP_LE_SWIZZLE, (addr))
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#define find_first_zero_le_bit(addr, size) find_next_zero_le_bit((addr), (size), 0)
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unsigned long find_next_zero_le_bit(const unsigned long *addr,
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unsigned long size, unsigned long offset);
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/* Bitmap functions for the ext2 filesystem */
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#define ext2_set_bit(nr,addr) \
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__test_and_set_le_bit((nr), (unsigned long*)addr)
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#define ext2_clear_bit(nr, addr) \
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__test_and_clear_le_bit((nr), (unsigned long*)addr)
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#define ext2_set_bit_atomic(lock, nr, addr) \
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test_and_set_le_bit((nr), (unsigned long*)addr)
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#define ext2_clear_bit_atomic(lock, nr, addr) \
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test_and_clear_le_bit((nr), (unsigned long*)addr)
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#define ext2_test_bit(nr, addr) test_le_bit((nr),(unsigned long*)addr)
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#define ext2_find_first_zero_bit(addr, size) \
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find_first_zero_le_bit((unsigned long*)addr, size)
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#define ext2_find_next_zero_bit(addr, size, off) \
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find_next_zero_le_bit((unsigned long*)addr, size, off)
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/* Bitmap functions for the minix filesystem. */
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#define minix_test_and_set_bit(nr,addr) \
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__test_and_set_le_bit(nr, (unsigned long *)addr)
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#define minix_set_bit(nr,addr) \
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__set_le_bit(nr, (unsigned long *)addr)
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#define minix_test_and_clear_bit(nr,addr) \
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__test_and_clear_le_bit(nr, (unsigned long *)addr)
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#define minix_test_bit(nr,addr) \
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test_le_bit(nr, (unsigned long *)addr)
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#define minix_find_first_zero_bit(addr,size) \
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find_first_zero_le_bit((unsigned long *)addr, size)
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/*
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* Every architecture must define this function. It's the fastest
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* way of searching a 140-bit bitmap where the first 100 bits are
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* unlikely to be set. It's guaranteed that at least one of the 140
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* bits is cleared.
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*/
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static inline int sched_find_first_bit(const unsigned long *b)
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{
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#ifdef CONFIG_PPC64
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if (unlikely(b[0]))
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return __ffs(b[0]);
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if (unlikely(b[1]))
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return __ffs(b[1]) + 64;
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return __ffs(b[2]) + 128;
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#else
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if (unlikely(b[0]))
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return __ffs(b[0]);
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if (unlikely(b[1]))
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return __ffs(b[1]) + 32;
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if (unlikely(b[2]))
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return __ffs(b[2]) + 64;
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if (b[3])
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return __ffs(b[3]) + 96;
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return __ffs(b[4]) + 128;
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#endif
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}
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_BITOPS_H */
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