f9569e1d15
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
428 lines
12 KiB
C
428 lines
12 KiB
C
/*
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* linux/include/asm-m68k/io.h
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*
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* 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
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* IO access
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* - added Q40 support
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* - added skeleton for GG-II and Amiga PCMCIA
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* 2/3/01 RZ: - moved a few more defs into raw_io.h
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*
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* inX/outX/readX/writeX should not be used by any driver unless it does
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* ISA or PCI access. Other drivers should use function defined in raw_io.h
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* or define its own macros on top of these.
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*
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* inX(),outX() are for PCI and ISA I/O
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* readX(),writeX() are for PCI memory
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* isa_readX(),isa_writeX() are for ISA memory
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*
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* moved mem{cpy,set}_*io inside CONFIG_PCI
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*/
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#ifndef _IO_H
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#define _IO_H
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#ifdef __KERNEL__
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#include <linux/compiler.h>
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#include <asm/raw_io.h>
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#include <asm/virtconvert.h>
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#include <asm-generic/iomap.h>
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#ifdef CONFIG_ATARI
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#include <asm/atarihw.h>
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#endif
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/*
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* IO/MEM definitions for various ISA bridges
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*/
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#ifdef CONFIG_Q40
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#define q40_isa_io_base 0xff400000
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#define q40_isa_mem_base 0xff800000
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#define Q40_ISA_IO_B(ioaddr) (q40_isa_io_base+1+4*((unsigned long)(ioaddr)))
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#define Q40_ISA_IO_W(ioaddr) (q40_isa_io_base+ 4*((unsigned long)(ioaddr)))
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#define Q40_ISA_MEM_B(madr) (q40_isa_mem_base+1+4*((unsigned long)(madr)))
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#define Q40_ISA_MEM_W(madr) (q40_isa_mem_base+ 4*((unsigned long)(madr)))
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#define MULTI_ISA 0
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#endif /* Q40 */
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/* GG-II Zorro to ISA bridge */
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#ifdef CONFIG_GG2
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extern unsigned long gg2_isa_base;
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#define GG2_ISA_IO_B(ioaddr) (gg2_isa_base+1+((unsigned long)(ioaddr)*4))
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#define GG2_ISA_IO_W(ioaddr) (gg2_isa_base+ ((unsigned long)(ioaddr)*4))
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#define GG2_ISA_MEM_B(madr) (gg2_isa_base+1+(((unsigned long)(madr)*4) & 0xfffff))
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#define GG2_ISA_MEM_W(madr) (gg2_isa_base+ (((unsigned long)(madr)*4) & 0xfffff))
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#ifndef MULTI_ISA
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#define MULTI_ISA 0
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#else
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#undef MULTI_ISA
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#define MULTI_ISA 1
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#endif
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#endif /* GG2 */
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#ifdef CONFIG_AMIGA_PCMCIA
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#include <asm/amigayle.h>
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#define AG_ISA_IO_B(ioaddr) ( GAYLE_IO+(ioaddr)+(((ioaddr)&1)*GAYLE_ODD) )
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#define AG_ISA_IO_W(ioaddr) ( GAYLE_IO+(ioaddr) )
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#ifndef MULTI_ISA
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#define MULTI_ISA 0
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#else
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#undef MULTI_ISA
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#define MULTI_ISA 1
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#endif
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#endif /* AMIGA_PCMCIA */
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#ifdef CONFIG_ISA
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#if MULTI_ISA == 0
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#undef MULTI_ISA
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#endif
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#define Q40_ISA (1)
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#define GG2_ISA (2)
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#define AG_ISA (3)
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#if defined(CONFIG_Q40) && !defined(MULTI_ISA)
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#define ISA_TYPE Q40_ISA
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#define ISA_SEX 0
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#endif
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#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
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#define ISA_TYPE AG_ISA
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#define ISA_SEX 1
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#endif
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#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
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#define ISA_TYPE GG2_ISA
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#define ISA_SEX 0
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#endif
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#ifdef MULTI_ISA
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extern int isa_type;
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extern int isa_sex;
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#define ISA_TYPE isa_type
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#define ISA_SEX isa_sex
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#endif
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/*
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* define inline addr translation functions. Normally only one variant will
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* be compiled in so the case statement will be optimised away
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*/
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static inline u8 __iomem *isa_itb(unsigned long addr)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_Q40
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case Q40_ISA: return (u8 __iomem *)Q40_ISA_IO_B(addr);
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#endif
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#ifdef CONFIG_GG2
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case GG2_ISA: return (u8 __iomem *)GG2_ISA_IO_B(addr);
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#endif
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: return (u8 __iomem *)AG_ISA_IO_B(addr);
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#endif
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default: return NULL; /* avoid warnings, just in case */
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}
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}
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static inline u16 __iomem *isa_itw(unsigned long addr)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_Q40
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case Q40_ISA: return (u16 __iomem *)Q40_ISA_IO_W(addr);
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#endif
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#ifdef CONFIG_GG2
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case GG2_ISA: return (u16 __iomem *)GG2_ISA_IO_W(addr);
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#endif
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: return (u16 __iomem *)AG_ISA_IO_W(addr);
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#endif
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default: return NULL; /* avoid warnings, just in case */
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}
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}
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static inline u32 __iomem *isa_itl(unsigned long addr)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: return (u32 __iomem *)AG_ISA_IO_W(addr);
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#endif
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default: return 0; /* avoid warnings, just in case */
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}
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}
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static inline u8 __iomem *isa_mtb(unsigned long addr)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_Q40
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case Q40_ISA: return (u8 __iomem *)Q40_ISA_MEM_B(addr);
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#endif
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#ifdef CONFIG_GG2
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case GG2_ISA: return (u8 __iomem *)GG2_ISA_MEM_B(addr);
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#endif
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: return (u8 __iomem *)addr;
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#endif
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default: return NULL; /* avoid warnings, just in case */
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}
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}
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static inline u16 __iomem *isa_mtw(unsigned long addr)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_Q40
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case Q40_ISA: return (u16 __iomem *)Q40_ISA_MEM_W(addr);
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#endif
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#ifdef CONFIG_GG2
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case GG2_ISA: return (u16 __iomem *)GG2_ISA_MEM_W(addr);
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#endif
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: return (u16 __iomem *)addr;
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#endif
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default: return NULL; /* avoid warnings, just in case */
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}
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}
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#define isa_inb(port) in_8(isa_itb(port))
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#define isa_inw(port) (ISA_SEX ? in_be16(isa_itw(port)) : in_le16(isa_itw(port)))
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#define isa_inl(port) (ISA_SEX ? in_be32(isa_itl(port)) : in_le32(isa_itl(port)))
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#define isa_outb(val,port) out_8(isa_itb(port),(val))
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#define isa_outw(val,port) (ISA_SEX ? out_be16(isa_itw(port),(val)) : out_le16(isa_itw(port),(val)))
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#define isa_outl(val,port) (ISA_SEX ? out_be32(isa_itl(port),(val)) : out_le32(isa_itl(port),(val)))
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#define isa_readb(p) in_8(isa_mtb((unsigned long)(p)))
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#define isa_readw(p) \
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(ISA_SEX ? in_be16(isa_mtw((unsigned long)(p))) \
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: in_le16(isa_mtw((unsigned long)(p))))
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#define isa_writeb(val,p) out_8(isa_mtb((unsigned long)(p)),(val))
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#define isa_writew(val,p) \
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(ISA_SEX ? out_be16(isa_mtw((unsigned long)(p)),(val)) \
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: out_le16(isa_mtw((unsigned long)(p)),(val)))
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static inline void isa_delay(void)
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{
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switch(ISA_TYPE)
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{
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#ifdef CONFIG_Q40
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case Q40_ISA: isa_outb(0,0x80); break;
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#endif
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#ifdef CONFIG_GG2
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case GG2_ISA: break;
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#endif
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#ifdef CONFIG_AMIGA_PCMCIA
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case AG_ISA: break;
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#endif
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default: break; /* avoid warnings */
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}
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}
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#define isa_inb_p(p) ({u8 v=isa_inb(p);isa_delay();v;})
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#define isa_outb_p(v,p) ({isa_outb((v),(p));isa_delay();})
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#define isa_inw_p(p) ({u16 v=isa_inw(p);isa_delay();v;})
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#define isa_outw_p(v,p) ({isa_outw((v),(p));isa_delay();})
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#define isa_inl_p(p) ({u32 v=isa_inl(p);isa_delay();v;})
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#define isa_outl_p(v,p) ({isa_outl((v),(p));isa_delay();})
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#define isa_insb(port, buf, nr) raw_insb(isa_itb(port), (u8 *)(buf), (nr))
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#define isa_outsb(port, buf, nr) raw_outsb(isa_itb(port), (u8 *)(buf), (nr))
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#define isa_insw(port, buf, nr) \
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(ISA_SEX ? raw_insw(isa_itw(port), (u16 *)(buf), (nr)) : \
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raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
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#define isa_outsw(port, buf, nr) \
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(ISA_SEX ? raw_outsw(isa_itw(port), (u16 *)(buf), (nr)) : \
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raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)))
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#define isa_insl(port, buf, nr) \
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(ISA_SEX ? raw_insl(isa_itl(port), (u32 *)(buf), (nr)) : \
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raw_insw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
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#define isa_outsl(port, buf, nr) \
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(ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) : \
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raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
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#endif /* CONFIG_ISA */
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#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
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#define inb isa_inb
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#define inb_p isa_inb_p
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#define outb isa_outb
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#define outb_p isa_outb_p
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#define inw isa_inw
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#define inw_p isa_inw_p
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#define outw isa_outw
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#define outw_p isa_outw_p
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#define inl isa_inl
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#define inl_p isa_inl_p
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#define outl isa_outl
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#define outl_p isa_outl_p
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#define insb isa_insb
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#define insw isa_insw
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#define insl isa_insl
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#define outsb isa_outsb
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#define outsw isa_outsw
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#define outsl isa_outsl
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#define readb isa_readb
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#define readw isa_readw
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#define writeb isa_writeb
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#define writew isa_writew
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#endif /* CONFIG_ISA */
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#if defined(CONFIG_PCI)
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#define readl(addr) in_le32(addr)
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#define writel(val,addr) out_le32((addr),(val))
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/* those can be defined for both ISA and PCI - it won't work though */
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#define readb(addr) in_8(addr)
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#define readw(addr) in_le16(addr)
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#define writeb(val,addr) out_8((addr),(val))
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#define writew(val,addr) out_le16((addr),(val))
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#define readb_relaxed(addr) readb(addr)
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#define readw_relaxed(addr) readw(addr)
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#define readl_relaxed(addr) readl(addr)
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#ifndef CONFIG_ISA
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#define inb(port) in_8(port)
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#define outb(val,port) out_8((port),(val))
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#define inw(port) in_le16(port)
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#define outw(val,port) out_le16((port),(val))
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#define inl(port) in_le32(port)
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#define outl(val,port) out_le32((port),(val))
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#else
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/*
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* kernel with both ISA and PCI compiled in, those have
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* conflicting defs for in/out. Simply consider port < 1024
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* ISA and everything else PCI. read,write not defined
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* in this case
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*/
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#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
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#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
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#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
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#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
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#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
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#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))
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#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
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#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
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#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
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#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
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#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
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#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
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#endif
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#endif /* CONFIG_PCI */
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#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
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/*
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* We need to define dummy functions for GENERIC_IOMAP support.
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*/
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#define inb(port) 0xff
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#define inb_p(port) 0xff
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#define outb(val,port) ((void)0)
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#define outb_p(val,port) ((void)0)
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#define inw(port) 0xffff
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#define outw(val,port) ((void)0)
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#define inl(port) 0xffffffffUL
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#define outl(val,port) ((void)0)
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#define insb(port,buf,nr) ((void)0)
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#define outsb(port,buf,nr) ((void)0)
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#define insw(port,buf,nr) ((void)0)
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#define outsw(port,buf,nr) ((void)0)
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#define insl(port,buf,nr) ((void)0)
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#define outsl(port,buf,nr) ((void)0)
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/*
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* These should be valid on any ioremap()ed region
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*/
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#define readb(addr) in_8(addr)
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#define writeb(val,addr) out_8((addr),(val))
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#define readw(addr) in_le16(addr)
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#define writew(val,addr) out_le16((addr),(val))
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#endif
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#if !defined(CONFIG_PCI)
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#define readl(addr) in_le32(addr)
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#define writel(val,addr) out_le32((addr),(val))
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#endif
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#define mmiowb()
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static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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static inline void __iomem *ioremap_nocache(unsigned long physaddr, unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
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}
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static inline void __iomem *ioremap_writethrough(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_WRITETHROUGH);
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}
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static inline void __iomem *ioremap_fullcache(unsigned long physaddr,
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unsigned long size)
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{
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return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
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}
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/* m68k caches aren't DMA coherent */
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extern void dma_cache_wback_inv(unsigned long start, unsigned long size);
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extern void dma_cache_wback(unsigned long start, unsigned long size);
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extern void dma_cache_inv(unsigned long start, unsigned long size);
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static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
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{
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__builtin_memset((void __force *) addr, val, count);
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}
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static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
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{
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__builtin_memcpy(dst, (void __force *) src, count);
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}
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static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
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{
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__builtin_memcpy((void __force *) dst, src, count);
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}
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#ifndef CONFIG_SUN3
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#define IO_SPACE_LIMIT 0xffff
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#else
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#define IO_SPACE_LIMIT 0x0fffffff
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#endif
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#endif /* __KERNEL__ */
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#define __ARCH_HAS_NO_PAGE_ZERO_MAPPED 1
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#endif /* _IO_H */
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