59c422358d
Increase the maximum system size of SGI SN systems. Note that this is not the maximum SSI size. The maximum system size is the number of nodes in the numalink domain. Signed-off-by: Jack Steiner <steiner@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
85 lines
2.6 KiB
C
85 lines
2.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* SGI specific setup.
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*
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* Copyright (C) 1995-1997,1999,2001-2005 Silicon Graphics, Inc. All rights reserved.
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* Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
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*/
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#ifndef _ASM_IA64_SN_ARCH_H
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#define _ASM_IA64_SN_ARCH_H
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#include <linux/numa.h>
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#include <asm/types.h>
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#include <asm/percpu.h>
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#include <asm/sn/types.h>
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#include <asm/sn/sn_cpuid.h>
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/*
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* This is the maximum number of NUMALINK nodes that can be part of a single
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* SSI kernel. This number includes C-brick, M-bricks, and TIOs. Nodes in
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* remote partitions are NOT included in this number.
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* The number of compact nodes cannot exceed size of a coherency domain.
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* The purpose of this define is to specify a node count that includes
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* all C/M/TIO nodes in an SSI system.
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*
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* SGI system can currently support up to 256 C/M nodes plus additional TIO nodes.
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*
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* Note: ACPI20 has an architectural limit of 256 nodes. When we upgrade
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* to ACPI3.0, this limit will be removed. The notion of "compact nodes"
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* should be deleted and TIOs should be included in MAX_NUMNODES.
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*/
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#define MAX_COMPACT_NODES 512
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/*
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* Maximum number of nodes in all partitions and in all coherency domains.
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* This is the total number of nodes accessible in the numalink fabric. It
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* includes all C & M bricks, plus all TIOs.
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*
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* This value is also the value of the maximum number of NASIDs in the numalink
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* fabric.
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*/
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#define MAX_NUMALINK_NODES 16384
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/*
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* The following defines attributes of the HUB chip. These attributes are
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* frequently referenced. They are kept in the per-cpu data areas of each cpu.
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* They are kept together in a struct to minimize cache misses.
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*/
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struct sn_hub_info_s {
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u8 shub2;
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u8 nasid_shift;
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u8 as_shift;
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u8 shub_1_1_found;
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u16 nasid_bitmask;
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};
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DECLARE_PER_CPU(struct sn_hub_info_s, __sn_hub_info);
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#define sn_hub_info (&__get_cpu_var(__sn_hub_info))
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#define is_shub2() (sn_hub_info->shub2)
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#define is_shub1() (sn_hub_info->shub2 == 0)
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/*
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* Use this macro to test if shub 1.1 wars should be enabled
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*/
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#define enable_shub_wars_1_1() (sn_hub_info->shub_1_1_found)
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/*
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* Compact node ID to nasid mappings kept in the per-cpu data areas of each
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* cpu.
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*/
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DECLARE_PER_CPU(short, __sn_cnodeid_to_nasid[MAX_NUMNODES]);
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#define sn_cnodeid_to_nasid (&__get_cpu_var(__sn_cnodeid_to_nasid[0]))
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extern u8 sn_partition_id;
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extern u8 sn_system_size;
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extern u8 sn_sharing_domain_size;
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extern u8 sn_region_size;
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extern void sn_flush_all_caches(long addr, long bytes);
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#endif /* _ASM_IA64_SN_ARCH_H */
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