a7b9403f0e
Now that we have 64-bits for PMDs we can stop using special encodings for the huge PMD values, and just put real PTEs in there. We allocate a _PAGE_PMD_HUGE bit to distinguish between plain PMDs and huge ones. It is the same for both 4U and 4V PTE layouts. We also use _PAGE_SPECIAL to indicate the splitting state, since a huge PMD cannot also be special. All of the PMD --> PTE translation code disappears, and most of the huge PMD bit modifications and tests just degenerate into the PTE operations. In particular USER_PGTABLE_CHECK_PMD_HUGE becomes trivial. As a side effect, normal PMDs don't shift the physical address around. This also speeds up the page table walks in the TLB miss paths since they don't have to do the shifts any more. Another non-trivial aspect is that pte_modify() has to be changed to preserve the _PAGE_PMD_HUGE bits as well as the page size field of the pte. Signed-off-by: David S. Miller <davem@davemloft.net>
231 lines
4.6 KiB
C
231 lines
4.6 KiB
C
/* arch/sparc64/mm/tlb.c
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*
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* Copyright (C) 2004 David S. Miller <davem@redhat.com>
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/percpu.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/preempt.h>
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#include <asm/pgtable.h>
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#include <asm/pgalloc.h>
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#include <asm/tlbflush.h>
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#include <asm/cacheflush.h>
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#include <asm/mmu_context.h>
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#include <asm/tlb.h>
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/* Heavily inspired by the ppc64 code. */
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static DEFINE_PER_CPU(struct tlb_batch, tlb_batch);
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void flush_tlb_pending(void)
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{
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struct tlb_batch *tb = &get_cpu_var(tlb_batch);
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struct mm_struct *mm = tb->mm;
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if (!tb->tlb_nr)
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goto out;
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flush_tsb_user(tb);
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if (CTX_VALID(mm->context)) {
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if (tb->tlb_nr == 1) {
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global_flush_tlb_page(mm, tb->vaddrs[0]);
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} else {
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#ifdef CONFIG_SMP
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smp_flush_tlb_pending(tb->mm, tb->tlb_nr,
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&tb->vaddrs[0]);
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#else
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__flush_tlb_pending(CTX_HWBITS(tb->mm->context),
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tb->tlb_nr, &tb->vaddrs[0]);
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#endif
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}
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}
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tb->tlb_nr = 0;
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out:
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put_cpu_var(tlb_batch);
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}
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void arch_enter_lazy_mmu_mode(void)
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{
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struct tlb_batch *tb = &__get_cpu_var(tlb_batch);
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tb->active = 1;
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}
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void arch_leave_lazy_mmu_mode(void)
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{
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struct tlb_batch *tb = &__get_cpu_var(tlb_batch);
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if (tb->tlb_nr)
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flush_tlb_pending();
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tb->active = 0;
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}
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static void tlb_batch_add_one(struct mm_struct *mm, unsigned long vaddr,
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bool exec)
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{
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struct tlb_batch *tb = &get_cpu_var(tlb_batch);
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unsigned long nr;
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vaddr &= PAGE_MASK;
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if (exec)
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vaddr |= 0x1UL;
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nr = tb->tlb_nr;
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if (unlikely(nr != 0 && mm != tb->mm)) {
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flush_tlb_pending();
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nr = 0;
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}
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if (!tb->active) {
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flush_tsb_user_page(mm, vaddr);
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global_flush_tlb_page(mm, vaddr);
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goto out;
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}
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if (nr == 0)
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tb->mm = mm;
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tb->vaddrs[nr] = vaddr;
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tb->tlb_nr = ++nr;
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if (nr >= TLB_BATCH_NR)
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flush_tlb_pending();
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out:
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put_cpu_var(tlb_batch);
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}
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void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
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pte_t *ptep, pte_t orig, int fullmm)
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{
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if (tlb_type != hypervisor &&
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pte_dirty(orig)) {
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unsigned long paddr, pfn = pte_pfn(orig);
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struct address_space *mapping;
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struct page *page;
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if (!pfn_valid(pfn))
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goto no_cache_flush;
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page = pfn_to_page(pfn);
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if (PageReserved(page))
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goto no_cache_flush;
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/* A real file page? */
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mapping = page_mapping(page);
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if (!mapping)
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goto no_cache_flush;
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paddr = (unsigned long) page_address(page);
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if ((paddr ^ vaddr) & (1 << 13))
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flush_dcache_page_all(mm, page);
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}
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no_cache_flush:
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if (!fullmm)
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tlb_batch_add_one(mm, vaddr, pte_exec(orig));
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}
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#ifdef CONFIG_TRANSPARENT_HUGEPAGE
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static void tlb_batch_pmd_scan(struct mm_struct *mm, unsigned long vaddr,
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pmd_t pmd, bool exec)
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{
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unsigned long end;
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pte_t *pte;
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pte = pte_offset_map(&pmd, vaddr);
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end = vaddr + HPAGE_SIZE;
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while (vaddr < end) {
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if (pte_val(*pte) & _PAGE_VALID)
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tlb_batch_add_one(mm, vaddr, exec);
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pte++;
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vaddr += PAGE_SIZE;
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}
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pte_unmap(pte);
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}
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void set_pmd_at(struct mm_struct *mm, unsigned long addr,
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pmd_t *pmdp, pmd_t pmd)
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{
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pmd_t orig = *pmdp;
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*pmdp = pmd;
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if (mm == &init_mm)
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return;
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if ((pmd_val(pmd) ^ pmd_val(orig)) & _PAGE_PMD_HUGE) {
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if (pmd_val(pmd) & _PAGE_PMD_HUGE)
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mm->context.huge_pte_count++;
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else
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mm->context.huge_pte_count--;
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/* Do not try to allocate the TSB hash table if we
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* don't have one already. We have various locks held
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* and thus we'll end up doing a GFP_KERNEL allocation
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* in an atomic context.
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*
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* Instead, we let the first TLB miss on a hugepage
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* take care of this.
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*/
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}
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if (!pmd_none(orig)) {
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pte_t orig_pte = __pte(pmd_val(orig));
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bool exec = pte_exec(orig_pte);
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addr &= HPAGE_MASK;
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if (pmd_trans_huge(orig)) {
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tlb_batch_add_one(mm, addr, exec);
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tlb_batch_add_one(mm, addr + REAL_HPAGE_SIZE, exec);
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} else {
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tlb_batch_pmd_scan(mm, addr, orig, exec);
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}
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}
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}
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void pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
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pgtable_t pgtable)
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{
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struct list_head *lh = (struct list_head *) pgtable;
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assert_spin_locked(&mm->page_table_lock);
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/* FIFO */
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if (!mm->pmd_huge_pte)
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INIT_LIST_HEAD(lh);
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else
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list_add(lh, (struct list_head *) mm->pmd_huge_pte);
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mm->pmd_huge_pte = pgtable;
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}
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pgtable_t pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
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{
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struct list_head *lh;
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pgtable_t pgtable;
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assert_spin_locked(&mm->page_table_lock);
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/* FIFO */
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pgtable = mm->pmd_huge_pte;
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lh = (struct list_head *) pgtable;
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if (list_empty(lh))
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mm->pmd_huge_pte = NULL;
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else {
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mm->pmd_huge_pte = (pgtable_t) lh->next;
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list_del(lh);
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}
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pte_val(pgtable[0]) = 0;
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pte_val(pgtable[1]) = 0;
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return pgtable;
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}
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#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
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