fb1c8f93d8
This patch (written by me and also containing many suggestions of Arjan van de Ven) does a major cleanup of the spinlock code. It does the following things: - consolidates and enhances the spinlock/rwlock debugging code - simplifies the asm/spinlock.h files - encapsulates the raw spinlock type and moves generic spinlock features (such as ->break_lock) into the generic code. - cleans up the spinlock code hierarchy to get rid of the spaghetti. Most notably there's now only a single variant of the debugging code, located in lib/spinlock_debug.c. (previously we had one SMP debugging variant per architecture, plus a separate generic one for UP builds) Also, i've enhanced the rwlock debugging facility, it will now track write-owners. There is new spinlock-owner/CPU-tracking on SMP builds too. All locks have lockup detection now, which will work for both soft and hard spin/rwlock lockups. The arch-level include files now only contain the minimally necessary subset of the spinlock code - all the rest that can be generalized now lives in the generic headers: include/asm-i386/spinlock_types.h | 16 include/asm-x86_64/spinlock_types.h | 16 I have also split up the various spinlock variants into separate files, making it easier to see which does what. The new layout is: SMP | UP ----------------------------|----------------------------------- asm/spinlock_types_smp.h | linux/spinlock_types_up.h linux/spinlock_types.h | linux/spinlock_types.h asm/spinlock_smp.h | linux/spinlock_up.h linux/spinlock_api_smp.h | linux/spinlock_api_up.h linux/spinlock.h | linux/spinlock.h /* * here's the role of the various spinlock/rwlock related include files: * * on SMP builds: * * asm/spinlock_types.h: contains the raw_spinlock_t/raw_rwlock_t and the * initializers * * linux/spinlock_types.h: * defines the generic type and initializers * * asm/spinlock.h: contains the __raw_spin_*()/etc. lowlevel * implementations, mostly inline assembly code * * (also included on UP-debug builds:) * * linux/spinlock_api_smp.h: * contains the prototypes for the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. * * on UP builds: * * linux/spinlock_type_up.h: * contains the generic, simplified UP spinlock type. * (which is an empty structure on non-debug builds) * * linux/spinlock_types.h: * defines the generic type and initializers * * linux/spinlock_up.h: * contains the __raw_spin_*()/etc. version of UP * builds. (which are NOPs on non-debug, non-preempt * builds) * * (included on UP-non-debug builds:) * * linux/spinlock_api_up.h: * builds the _spin_*() APIs. * * linux/spinlock.h: builds the final spin_*() APIs. */ All SMP and UP architectures are converted by this patch. arm, i386, ia64, ppc, ppc64, s390/s390x, x64 was build-tested via crosscompilers. m32r, mips, sh, sparc, have not been tested yet, but should be mostly fine. From: Grant Grundler <grundler@parisc-linux.org> Booted and lightly tested on a500-44 (64-bit, SMP kernel, dual CPU). Builds 32-bit SMP kernel (not booted or tested). I did not try to build non-SMP kernels. That should be trivial to fix up later if necessary. I converted bit ops atomic_hash lock to raw_spinlock_t. Doing so avoids some ugly nesting of linux/*.h and asm/*.h files. Those particular locks are well tested and contained entirely inside arch specific code. I do NOT expect any new issues to arise with them. If someone does ever need to use debug/metrics with them, then they will need to unravel this hairball between spinlocks, atomic ops, and bit ops that exist only because parisc has exactly one atomic instruction: LDCW (load and clear word). From: "Luck, Tony" <tony.luck@intel.com> ia64 fix Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Arjan van de Ven <arjanv@infradead.org> Signed-off-by: Grant Grundler <grundler@parisc-linux.org> Cc: Matthew Wilcox <willy@debian.org> Signed-off-by: Hirokazu Takata <takata@linux-m32r.org> Signed-off-by: Mikael Pettersson <mikpe@csd.uu.se> Signed-off-by: Benoit Boissinot <benoit.boissinot@ens-lyon.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
141 lines
3.4 KiB
C
141 lines
3.4 KiB
C
/* spinlock.h: 32-bit Sparc spinlock support.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef __SPARC_SPINLOCK_H
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#define __SPARC_SPINLOCK_H
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#include <linux/threads.h> /* For NR_CPUS */
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#ifndef __ASSEMBLY__
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#include <asm/psr.h>
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#define __raw_spin_is_locked(lock) (*((volatile unsigned char *)(lock)) != 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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extern __inline__ void __raw_spin_lock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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"\n1:\n\t"
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"ldstub [%0], %%g2\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2f\n\t"
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" ldub [%0], %%g2\n\t"
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".subsection 2\n"
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"2:\n\t"
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"orcc %%g2, 0x0, %%g0\n\t"
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"bne,a 2b\n\t"
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" ldub [%0], %%g2\n\t"
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"b,a 1b\n\t"
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".previous\n"
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: /* no outputs */
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: "r" (lock)
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: "g2", "memory", "cc");
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}
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extern __inline__ int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned int result;
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__asm__ __volatile__("ldstub [%1], %0"
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: "=r" (result)
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: "r" (lock)
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: "memory");
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return (result == 0);
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}
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extern __inline__ void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__("stb %%g0, [%0]" : : "r" (lock) : "memory");
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}
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/* Read-write spinlocks, allowing multiple readers
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* but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts
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* but no interrupt writers. For those circumstances we
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* can "mix" irq-safe locks - any writer needs to get a
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* irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*
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* XXX This might create some problems with my dual spinlock
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* XXX scheme, deadlocks etc. -DaveM
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*
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* Sort of like atomic_t's on Sparc, but even more clever.
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*
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* ------------------------------------
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* | 24-bit counter | wlock | raw_rwlock_t
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* ------------------------------------
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* 31 8 7 0
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*
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* wlock signifies the one writer is in or somebody is updating
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* counter. For a writer, if he successfully acquires the wlock,
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* but counter is non-zero, he has to release the lock and wait,
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* till both counter and wlock are zero.
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*
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* Unfortunately this scheme limits us to ~16,000,000 cpus.
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*/
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extern __inline__ void __read_lock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define __raw_read_lock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__raw_read_lock(lock); \
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local_irq_restore(flags); \
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} while(0)
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extern __inline__ void __read_unlock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_read_exit\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define __raw_read_unlock(lock) \
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do { unsigned long flags; \
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local_irq_save(flags); \
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__raw_read_unlock(lock); \
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local_irq_restore(flags); \
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} while(0)
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extern __inline__ void __raw_write_lock(raw_rwlock_t *rw)
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{
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register raw_rwlock_t *lp asm("g1");
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lp = rw;
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__asm__ __volatile__(
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"mov %%o7, %%g4\n\t"
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"call ___rw_write_enter\n\t"
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" ldstub [%%g1 + 3], %%g2\n"
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: /* no outputs */
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: "r" (lp)
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: "g2", "g4", "memory", "cc");
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}
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#define __raw_write_unlock(rw) do { (rw)->lock = 0; } while(0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#endif /* !(__ASSEMBLY__) */
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#endif /* __SPARC_SPINLOCK_H */
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