7bd40c16cc
We've always been able to use either method on VLV, but it appears more recent BIOSes only support the gen6 method, so switch over to that. References: https://bugs.freedesktop.org/show_bug.cgi?id=71370 Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
489 lines
13 KiB
C
489 lines
13 KiB
C
/* Various workarounds for chipset bugs.
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This code runs very early and can't use the regular PCI subsystem
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The entries are keyed to PCI bridges which usually identify chipsets
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uniquely.
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This is only for whole classes of chipsets with specific problems which
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need early invasive action (e.g. before the timers are initialized).
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Most PCI device specific workarounds can be done later and should be
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in standard PCI quirks
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Mainboard specific bugs should be handled by DMI entries.
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CPU specific bugs in setup.c */
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#include <linux/pci.h>
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#include <linux/acpi.h>
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#include <linux/pci_ids.h>
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#include <drm/i915_drm.h>
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#include <asm/pci-direct.h>
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#include <asm/dma.h>
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#include <asm/io_apic.h>
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#include <asm/apic.h>
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#include <asm/iommu.h>
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#include <asm/gart.h>
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#include <asm/irq_remapping.h>
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static void __init fix_hypertransport_config(int num, int slot, int func)
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{
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u32 htcfg;
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/*
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* we found a hypertransport bus
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* make sure that we are broadcasting
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* interrupts to all cpus on the ht bus
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* if we're using extended apic ids
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*/
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htcfg = read_pci_config(num, slot, func, 0x68);
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if (htcfg & (1 << 18)) {
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printk(KERN_INFO "Detected use of extended apic ids "
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"on hypertransport bus\n");
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if ((htcfg & (1 << 17)) == 0) {
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printk(KERN_INFO "Enabling hypertransport extended "
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"apic interrupt broadcast\n");
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printk(KERN_INFO "Note this is a bios bug, "
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"please contact your hw vendor\n");
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htcfg |= (1 << 17);
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write_pci_config(num, slot, func, 0x68, htcfg);
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}
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}
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}
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static void __init via_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_GART_IOMMU
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if ((max_pfn > MAX_DMA32_PFN || force_iommu) &&
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!gart_iommu_aperture_allowed) {
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printk(KERN_INFO
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"Looks like a VIA chipset. Disabling IOMMU."
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" Override with iommu=allowed\n");
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gart_iommu_aperture_disabled = 1;
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}
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#endif
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}
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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static int __init nvidia_hpet_check(struct acpi_table_header *header)
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{
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return 0;
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}
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#endif /* CONFIG_X86_IO_APIC */
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#endif /* CONFIG_ACPI */
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static void __init nvidia_bugs(int num, int slot, int func)
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{
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#ifdef CONFIG_ACPI
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#ifdef CONFIG_X86_IO_APIC
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/*
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* All timer overrides on Nvidia are
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* wrong unless HPET is enabled.
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* Unfortunately that's not true on many Asus boards.
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* We don't know yet how to detect this automatically, but
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* at least allow a command line override.
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*/
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if (acpi_use_timer_override)
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return;
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if (acpi_table_parse(ACPI_SIG_HPET, nvidia_hpet_check)) {
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acpi_skip_timer_override = 1;
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printk(KERN_INFO "Nvidia board "
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"detected. Ignoring ACPI "
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"timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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#endif
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#endif
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/* RED-PEN skip them on mptables too? */
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}
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#if defined(CONFIG_ACPI) && defined(CONFIG_X86_IO_APIC)
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static u32 __init ati_ixp4x0_rev(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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b = read_pci_config_byte(num, slot, func, 0xac);
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b &= ~(1<<5);
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write_pci_config_byte(num, slot, func, 0xac, b);
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d = read_pci_config(num, slot, func, 0x70);
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d |= 1<<8;
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write_pci_config(num, slot, func, 0x70, d);
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs(int num, int slot, int func)
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{
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u32 d;
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u8 b;
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if (acpi_use_timer_override)
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return;
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d = ati_ixp4x0_rev(num, slot, func);
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if (d < 0x82)
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acpi_skip_timer_override = 1;
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else {
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/* check for IRQ0 interrupt swap */
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outb(0x72, 0xcd6); b = inb(0xcd7);
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if (!(b & 0x2))
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acpi_skip_timer_override = 1;
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}
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB4X0 revision 0x%x\n", d);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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static u32 __init ati_sbx00_rev(int num, int slot, int func)
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{
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u32 d;
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d = read_pci_config(num, slot, func, 0x8);
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d &= 0xff;
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return d;
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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u32 d, rev;
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rev = ati_sbx00_rev(num, slot, func);
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if (rev >= 0x40)
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acpi_fix_pin2_polarity = 1;
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/*
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* SB600: revisions 0x11, 0x12, 0x13, 0x14, ...
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* SB700: revisions 0x39, 0x3a, ...
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* SB800: revisions 0x40, 0x41, ...
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*/
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if (rev >= 0x39)
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return;
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if (acpi_use_timer_override)
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return;
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/* check for IRQ0 interrupt swap */
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d = read_pci_config(num, slot, func, 0x64);
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if (!(d & (1<<14)))
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acpi_skip_timer_override = 1;
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if (acpi_skip_timer_override) {
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printk(KERN_INFO "SB600 revision 0x%x\n", rev);
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printk(KERN_INFO "Ignoring ACPI timer override.\n");
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printk(KERN_INFO "If you got timer trouble "
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"try acpi_use_timer_override\n");
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}
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}
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#else
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static void __init ati_bugs(int num, int slot, int func)
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{
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}
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static void __init ati_bugs_contd(int num, int slot, int func)
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{
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}
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#endif
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static void __init intel_remapping_check(int num, int slot, int func)
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{
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u8 revision;
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u16 device;
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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revision = read_pci_config_byte(num, slot, func, PCI_REVISION_ID);
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/*
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* Revision 13 of all triggering devices id in this quirk have
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* a problem draining interrupts when irq remapping is enabled,
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* and should be flagged as broken. Additionally revisions 0x12
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* and 0x22 of device id 0x3405 has this problem.
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*/
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if (revision == 0x13)
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set_irq_remapping_broken();
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else if ((device == 0x3405) &&
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((revision == 0x12) ||
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(revision == 0x22)))
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set_irq_remapping_broken();
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}
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/*
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* Systems with Intel graphics controllers set aside memory exclusively
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* for gfx driver use. This memory is not marked in the E820 as reserved
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* or as RAM, and so is subject to overlap from E820 manipulation later
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* in the boot process. On some systems, MMIO space is allocated on top,
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* despite the efforts of the "RAM buffer" approach, which simply rounds
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* memory boundaries up to 64M to try to catch space that may decode
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* as RAM and so is not suitable for MMIO.
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*
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* And yes, so far on current devices the base addr is always under 4G.
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*/
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static u32 __init intel_stolen_base(int num, int slot, int func)
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{
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u32 base;
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/*
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* For the PCI IDs in this quirk, the stolen base is always
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* in 0x5c, aka the BDSM register (yes that's really what
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* it's called).
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*/
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base = read_pci_config(num, slot, func, 0x5c);
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base &= ~((1<<20) - 1);
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return base;
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}
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#define KB(x) ((x) * 1024)
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#define MB(x) (KB (KB (x)))
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#define GB(x) (MB (KB (x)))
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static size_t __init gen3_stolen_size(int num, int slot, int func)
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{
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size_t stolen_size;
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(0, 0, 0, I830_GMCH_CTRL);
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switch (gmch_ctrl & I855_GMCH_GMS_MASK) {
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case I855_GMCH_GMS_STOLEN_1M:
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stolen_size = MB(1);
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break;
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case I855_GMCH_GMS_STOLEN_4M:
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stolen_size = MB(4);
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break;
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case I855_GMCH_GMS_STOLEN_8M:
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stolen_size = MB(8);
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break;
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case I855_GMCH_GMS_STOLEN_16M:
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stolen_size = MB(16);
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break;
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case I855_GMCH_GMS_STOLEN_32M:
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stolen_size = MB(32);
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break;
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case I915_GMCH_GMS_STOLEN_48M:
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stolen_size = MB(48);
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break;
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case I915_GMCH_GMS_STOLEN_64M:
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stolen_size = MB(64);
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break;
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case G33_GMCH_GMS_STOLEN_128M:
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stolen_size = MB(128);
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break;
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case G33_GMCH_GMS_STOLEN_256M:
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stolen_size = MB(256);
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break;
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case INTEL_GMCH_GMS_STOLEN_96M:
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stolen_size = MB(96);
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break;
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case INTEL_GMCH_GMS_STOLEN_160M:
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stolen_size = MB(160);
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break;
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case INTEL_GMCH_GMS_STOLEN_224M:
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stolen_size = MB(224);
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break;
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case INTEL_GMCH_GMS_STOLEN_352M:
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stolen_size = MB(352);
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break;
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default:
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stolen_size = 0;
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break;
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}
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return stolen_size;
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}
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static size_t __init gen6_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= SNB_GMCH_GMS_SHIFT;
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gmch_ctrl &= SNB_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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}
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static inline size_t gen8_stolen_size(int num, int slot, int func)
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{
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u16 gmch_ctrl;
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gmch_ctrl = read_pci_config_16(num, slot, func, SNB_GMCH_CTRL);
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gmch_ctrl >>= BDW_GMCH_GMS_SHIFT;
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gmch_ctrl &= BDW_GMCH_GMS_MASK;
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return gmch_ctrl << 25; /* 32 MB units */
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}
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typedef size_t (*stolen_size_fn)(int num, int slot, int func);
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static struct pci_device_id intel_stolen_ids[] __initdata = {
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INTEL_I915G_IDS(gen3_stolen_size),
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INTEL_I915GM_IDS(gen3_stolen_size),
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INTEL_I945G_IDS(gen3_stolen_size),
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INTEL_I945GM_IDS(gen3_stolen_size),
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INTEL_VLV_M_IDS(gen6_stolen_size),
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INTEL_VLV_D_IDS(gen6_stolen_size),
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INTEL_PINEVIEW_IDS(gen3_stolen_size),
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INTEL_I965G_IDS(gen3_stolen_size),
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INTEL_G33_IDS(gen3_stolen_size),
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INTEL_I965GM_IDS(gen3_stolen_size),
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INTEL_GM45_IDS(gen3_stolen_size),
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INTEL_G45_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_D_IDS(gen3_stolen_size),
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INTEL_IRONLAKE_M_IDS(gen3_stolen_size),
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INTEL_SNB_D_IDS(gen6_stolen_size),
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INTEL_SNB_M_IDS(gen6_stolen_size),
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INTEL_IVB_M_IDS(gen6_stolen_size),
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INTEL_IVB_D_IDS(gen6_stolen_size),
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INTEL_HSW_D_IDS(gen6_stolen_size),
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INTEL_HSW_M_IDS(gen6_stolen_size),
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INTEL_BDW_M_IDS(gen8_stolen_size),
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INTEL_BDW_D_IDS(gen8_stolen_size)
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};
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static void __init intel_graphics_stolen(int num, int slot, int func)
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{
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size_t size;
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int i;
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u32 start;
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u16 device, subvendor, subdevice;
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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subvendor = read_pci_config_16(num, slot, func,
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PCI_SUBSYSTEM_VENDOR_ID);
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subdevice = read_pci_config_16(num, slot, func, PCI_SUBSYSTEM_ID);
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for (i = 0; i < ARRAY_SIZE(intel_stolen_ids); i++) {
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if (intel_stolen_ids[i].device == device) {
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stolen_size_fn stolen_size =
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(stolen_size_fn)intel_stolen_ids[i].driver_data;
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size = stolen_size(num, slot, func);
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start = intel_stolen_base(num, slot, func);
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if (size && start) {
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/* Mark this space as reserved */
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e820_add_region(start, size, E820_RESERVED);
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sanitize_e820_map(e820.map,
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ARRAY_SIZE(e820.map),
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&e820.nr_map);
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}
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return;
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}
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}
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}
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#define QFLAG_APPLY_ONCE 0x1
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#define QFLAG_APPLIED 0x2
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#define QFLAG_DONE (QFLAG_APPLY_ONCE|QFLAG_APPLIED)
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struct chipset {
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u32 vendor;
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u32 device;
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u32 class;
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u32 class_mask;
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u32 flags;
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void (*f)(int num, int slot, int func);
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};
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/*
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* Only works for devices on the root bus. If you add any devices
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* not on bus 0 readd another loop level in early_quirks(). But
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* be careful because at least the Nvidia quirk here relies on
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* only matching on bus 0.
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*/
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static struct chipset early_qrk[] __initdata = {
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{ PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, nvidia_bugs },
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{ PCI_VENDOR_ID_VIA, PCI_ANY_ID,
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PCI_CLASS_BRIDGE_PCI, PCI_ANY_ID, QFLAG_APPLY_ONCE, via_bugs },
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{ PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_K8_NB,
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PCI_CLASS_BRIDGE_HOST, PCI_ANY_ID, 0, fix_hypertransport_config },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs },
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{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
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PCI_CLASS_SERIAL_SMBUS, PCI_ANY_ID, 0, ati_bugs_contd },
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{ PCI_VENDOR_ID_INTEL, 0x3403, PCI_CLASS_BRIDGE_HOST,
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PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
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{ PCI_VENDOR_ID_INTEL, 0x3405, PCI_CLASS_BRIDGE_HOST,
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PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
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{ PCI_VENDOR_ID_INTEL, 0x3406, PCI_CLASS_BRIDGE_HOST,
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PCI_BASE_CLASS_BRIDGE, 0, intel_remapping_check },
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{ PCI_VENDOR_ID_INTEL, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, PCI_ANY_ID,
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QFLAG_APPLY_ONCE, intel_graphics_stolen },
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{}
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};
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/**
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* check_dev_quirk - apply early quirks to a given PCI device
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* @num: bus number
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* @slot: slot number
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* @func: PCI function
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*
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* Check the vendor & device ID against the early quirks table.
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*
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* If the device is single function, let early_quirks() know so we don't
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* poke at this device again.
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*/
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static int __init check_dev_quirk(int num, int slot, int func)
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{
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u16 class;
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u16 vendor;
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u16 device;
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u8 type;
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int i;
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class = read_pci_config_16(num, slot, func, PCI_CLASS_DEVICE);
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if (class == 0xffff)
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return -1; /* no class, treat as single function */
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vendor = read_pci_config_16(num, slot, func, PCI_VENDOR_ID);
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device = read_pci_config_16(num, slot, func, PCI_DEVICE_ID);
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for (i = 0; early_qrk[i].f != NULL; i++) {
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if (((early_qrk[i].vendor == PCI_ANY_ID) ||
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(early_qrk[i].vendor == vendor)) &&
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((early_qrk[i].device == PCI_ANY_ID) ||
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(early_qrk[i].device == device)) &&
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(!((early_qrk[i].class ^ class) &
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early_qrk[i].class_mask))) {
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if ((early_qrk[i].flags &
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QFLAG_DONE) != QFLAG_DONE)
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early_qrk[i].f(num, slot, func);
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early_qrk[i].flags |= QFLAG_APPLIED;
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}
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}
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type = read_pci_config_byte(num, slot, func,
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PCI_HEADER_TYPE);
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if (!(type & 0x80))
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return -1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
void __init early_quirks(void)
|
|
{
|
|
int slot, func;
|
|
|
|
if (!early_pci_allowed())
|
|
return;
|
|
|
|
/* Poor man's PCI discovery */
|
|
/* Only scan the root bus */
|
|
for (slot = 0; slot < 32; slot++)
|
|
for (func = 0; func < 8; func++) {
|
|
/* Only probe function 0 on single fn devices */
|
|
if (check_dev_quirk(0, slot, func))
|
|
break;
|
|
}
|
|
}
|