1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
191 lines
3.8 KiB
C
191 lines
3.8 KiB
C
/*
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* arch/mips/ddb5476/nile4.c --
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* low-level PIC code for NEC Vrc-5476 (Nile 4)
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*
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* Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
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* Sony Software Development Center Europe (SDCE), Brussels
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: jsun@mvista.com or jsun@junsun.net
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*
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*/
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#include <linux/config.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <asm/addrspace.h>
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#include <asm/ddb5xxx/ddb5xxx.h>
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/*
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* Interrupt Programming
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*/
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void nile4_map_irq(int nile4_irq, int cpu_irq)
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{
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u32 offset, t;
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offset = DDB_INTCTRL;
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if (nile4_irq >= 8) {
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offset += 4;
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nile4_irq -= 8;
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}
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t = ddb_in32(offset);
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t &= ~(7 << (nile4_irq * 4));
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t |= cpu_irq << (nile4_irq * 4);
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ddb_out32(offset, t);
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}
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void nile4_map_irq_all(int cpu_irq)
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{
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u32 all, t;
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all = cpu_irq;
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all |= all << 4;
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all |= all << 8;
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all |= all << 16;
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t = ddb_in32(DDB_INTCTRL);
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t &= 0x88888888;
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t |= all;
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ddb_out32(DDB_INTCTRL, t);
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t = ddb_in32(DDB_INTCTRL + 4);
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t &= 0x88888888;
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t |= all;
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ddb_out32(DDB_INTCTRL + 4, t);
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}
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void nile4_enable_irq(int nile4_irq)
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{
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u32 offset, t;
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offset = DDB_INTCTRL;
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if (nile4_irq >= 8) {
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offset += 4;
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nile4_irq -= 8;
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}
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t = ddb_in32(offset);
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t |= 8 << (nile4_irq * 4);
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ddb_out32(offset, t);
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}
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void nile4_disable_irq(int nile4_irq)
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{
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u32 offset, t;
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offset = DDB_INTCTRL;
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if (nile4_irq >= 8) {
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offset += 4;
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nile4_irq -= 8;
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}
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t = ddb_in32(offset);
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t &= ~(8 << (nile4_irq * 4));
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ddb_out32(offset, t);
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}
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void nile4_disable_irq_all(void)
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{
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ddb_out32(DDB_INTCTRL, 0);
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ddb_out32(DDB_INTCTRL + 4, 0);
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}
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u16 nile4_get_irq_stat(int cpu_irq)
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{
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return ddb_in16(DDB_INTSTAT0 + cpu_irq * 2);
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}
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void nile4_enable_irq_output(int cpu_irq)
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{
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u32 t;
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t = ddb_in32(DDB_INTSTAT1 + 4);
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t |= 1 << (16 + cpu_irq);
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ddb_out32(DDB_INTSTAT1, t);
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}
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void nile4_disable_irq_output(int cpu_irq)
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{
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u32 t;
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t = ddb_in32(DDB_INTSTAT1 + 4);
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t &= ~(1 << (16 + cpu_irq));
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ddb_out32(DDB_INTSTAT1, t);
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}
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void nile4_set_pci_irq_polarity(int pci_irq, int high)
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{
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u32 t;
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t = ddb_in32(DDB_INTPPES);
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if (high)
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t &= ~(1 << (pci_irq * 2));
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else
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t |= 1 << (pci_irq * 2);
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ddb_out32(DDB_INTPPES, t);
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}
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void nile4_set_pci_irq_level_or_edge(int pci_irq, int level)
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{
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u32 t;
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t = ddb_in32(DDB_INTPPES);
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if (level)
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t |= 2 << (pci_irq * 2);
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else
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t &= ~(2 << (pci_irq * 2));
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ddb_out32(DDB_INTPPES, t);
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}
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void nile4_clear_irq(int nile4_irq)
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{
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ddb_out32(DDB_INTCLR, 1 << nile4_irq);
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}
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void nile4_clear_irq_mask(u32 mask)
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{
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ddb_out32(DDB_INTCLR, mask);
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}
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u8 nile4_i8259_iack(void)
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{
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u8 irq;
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u32 reg;
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/* Set window 0 for interrupt acknowledge */
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reg = ddb_in32(DDB_PCIINIT0);
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ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IACK, 0, DDB_PCI_ACCESS_32);
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irq = *(volatile u8 *) KSEG1ADDR(DDB_PCI_IACK_BASE);
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/* restore window 0 for PCI I/O space */
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// ddb_set_pmr(DDB_PCIINIT0, DDB_PCICMD_IO, 0, DDB_PCI_ACCESS_32);
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ddb_out32(DDB_PCIINIT0, reg);
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/* i8269.c set the base vector to be 0x0 */
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return irq + I8259_IRQ_BASE;
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}
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#if defined(CONFIG_RUNTIME_DEBUG)
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void nile4_dump_irq_status(void)
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{
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printk(KERN_DEBUG "
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CPUSTAT = %p:%p\n", (void *) ddb_in32(DDB_CPUSTAT + 4),
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(void *) ddb_in32(DDB_CPUSTAT));
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printk(KERN_DEBUG "
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INTCTRL = %p:%p\n", (void *) ddb_in32(DDB_INTCTRL + 4),
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(void *) ddb_in32(DDB_INTCTRL));
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printk(KERN_DEBUG
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"INTSTAT0 = %p:%p\n",
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(void *) ddb_in32(DDB_INTSTAT0 + 4),
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(void *) ddb_in32(DDB_INTSTAT0));
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printk(KERN_DEBUG
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"INTSTAT1 = %p:%p\n",
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(void *) ddb_in32(DDB_INTSTAT1 + 4),
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(void *) ddb_in32(DDB_INTSTAT1));
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printk(KERN_DEBUG
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"INTCLR = %p:%p\n", (void *) ddb_in32(DDB_INTCLR + 4),
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(void *) ddb_in32(DDB_INTCLR));
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printk(KERN_DEBUG
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"INTPPES = %p:%p\n", (void *) ddb_in32(DDB_INTPPES + 4),
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(void *) ddb_in32(DDB_INTPPES));
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}
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#endif
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