9a59f452ab
This file duplicates <linux/posix_acl_xattr.h>, using slightly different names. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
112 lines
3.3 KiB
C
112 lines
3.3 KiB
C
/*
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* arch/ppc/boot/common/mpc10x_common.c
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*
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* A routine to find out how much memory the machine has.
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*
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* Based on:
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* arch/ppc/kernel/mpc10x_common.c
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*
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* Author: Mark A. Greer
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* mgreer@mvista.com
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*
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* 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
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* the terms of the GNU General Public License version 2. This program
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* is licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*/
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#include <linux/pci.h>
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#include <asm/types.h>
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#include <asm/io.h>
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#include "mpc10x.h"
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/*
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* *** WARNING - A BAT MUST be set to access the PCI config addr/data regs ***
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*/
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/*
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* PCI config space macros, similar to indirect_xxx and early_xxx macros.
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* We assume bus 0.
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*/
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#define MPC10X_CFG_read(val, addr, type, op) *val = op((type)(addr))
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#define MPC10X_CFG_write(val, addr, type, op) op((type *)(addr), (val))
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#define MPC10X_PCI_OP(rw, size, type, op, mask) \
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static void \
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mpc10x_##rw##_config_##size(unsigned int __iomem *cfg_addr, \
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unsigned int *cfg_data, int devfn, int offset, \
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type val) \
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{ \
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out_be32(cfg_addr, \
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((offset & 0xfc) << 24) | (devfn << 16) \
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| (0 << 8) | 0x80); \
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MPC10X_CFG_##rw(val, cfg_data + (offset & mask), type, op); \
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return; \
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}
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MPC10X_PCI_OP(read, byte, u8 *, in_8, 3)
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MPC10X_PCI_OP(read, dword, u32 *, in_le32, 0)
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/*
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* Read the memory controller registers to determine the amount of memory in
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* the system. This assumes that the firmware has correctly set up the memory
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* controller registers. On CONFIG_PPC_PREP, we know we are being called
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* under a PReP memory map. On all other machines, we assume we are under
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* a CHRP memory map. Further, on CONFIG_PPC_MULTIPLATFORM we must rename
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* this function.
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*/
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#ifdef CONFIG_PPC_MULTIPLATFORM
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#define get_mem_size mpc10x_get_mem_size
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#endif
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unsigned long
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get_mem_size(void)
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{
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unsigned int *config_addr, *config_data, val;
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unsigned long start, end, total, offset;
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int i;
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unsigned char bank_enables;
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#ifdef CONFIG_PPC_PREP
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config_addr = (unsigned int *)MPC10X_MAPA_CNFG_ADDR;
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config_data = (unsigned int *)MPC10X_MAPA_CNFG_DATA;
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#else
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config_addr = (unsigned int *)MPC10X_MAPB_CNFG_ADDR;
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config_data = (unsigned int *)MPC10X_MAPB_CNFG_DATA;
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#endif
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mpc10x_read_config_byte(config_addr, config_data, PCI_DEVFN(0,0),
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MPC10X_MCTLR_MEM_BANK_ENABLES, &bank_enables);
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total = 0;
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for (i = 0; i < 8; i++) {
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if (bank_enables & (1 << i)) {
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offset = MPC10X_MCTLR_MEM_START_1 + ((i > 3) ? 4 : 0);
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mpc10x_read_config_dword(config_addr, config_data,
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PCI_DEVFN(0,0), offset, &val);
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start = (val >> ((i & 3) << 3)) & 0xff;
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offset = MPC10X_MCTLR_EXT_MEM_START_1 + ((i>3) ? 4 : 0);
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mpc10x_read_config_dword(config_addr, config_data,
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PCI_DEVFN(0,0), offset, &val);
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val = (val >> ((i & 3) << 3)) & 0x03;
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start = (val << 28) | (start << 20);
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offset = MPC10X_MCTLR_MEM_END_1 + ((i > 3) ? 4 : 0);
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mpc10x_read_config_dword(config_addr, config_data,
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PCI_DEVFN(0,0), offset, &val);
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end = (val >> ((i & 3) << 3)) & 0xff;
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offset = MPC10X_MCTLR_EXT_MEM_END_1 + ((i > 3) ? 4 : 0);
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mpc10x_read_config_dword(config_addr, config_data,
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PCI_DEVFN(0,0), offset, &val);
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val = (val >> ((i & 3) << 3)) & 0x03;
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end = (val << 28) | (end << 20) | 0xfffff;
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total += (end - start + 1);
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}
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}
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return total;
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}
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