1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
455 lines
15 KiB
C
455 lines
15 KiB
C
#ifndef __LINUX_UHCI_HCD_H
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#define __LINUX_UHCI_HCD_H
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#include <linux/list.h>
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#include <linux/usb.h>
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#define usb_packetid(pipe) (usb_pipein(pipe) ? USB_PID_IN : USB_PID_OUT)
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#define PIPE_DEVEP_MASK 0x0007ff00
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/*
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* Universal Host Controller Interface data structures and defines
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*/
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/* Command register */
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#define USBCMD 0
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#define USBCMD_RS 0x0001 /* Run/Stop */
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#define USBCMD_HCRESET 0x0002 /* Host reset */
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#define USBCMD_GRESET 0x0004 /* Global reset */
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#define USBCMD_EGSM 0x0008 /* Global Suspend Mode */
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#define USBCMD_FGR 0x0010 /* Force Global Resume */
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#define USBCMD_SWDBG 0x0020 /* SW Debug mode */
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#define USBCMD_CF 0x0040 /* Config Flag (sw only) */
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#define USBCMD_MAXP 0x0080 /* Max Packet (0 = 32, 1 = 64) */
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/* Status register */
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#define USBSTS 2
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#define USBSTS_USBINT 0x0001 /* Interrupt due to IOC */
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#define USBSTS_ERROR 0x0002 /* Interrupt due to error */
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#define USBSTS_RD 0x0004 /* Resume Detect */
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#define USBSTS_HSE 0x0008 /* Host System Error - basically PCI problems */
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#define USBSTS_HCPE 0x0010 /* Host Controller Process Error - the scripts were buggy */
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#define USBSTS_HCH 0x0020 /* HC Halted */
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/* Interrupt enable register */
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#define USBINTR 4
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#define USBINTR_TIMEOUT 0x0001 /* Timeout/CRC error enable */
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#define USBINTR_RESUME 0x0002 /* Resume interrupt enable */
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#define USBINTR_IOC 0x0004 /* Interrupt On Complete enable */
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#define USBINTR_SP 0x0008 /* Short packet interrupt enable */
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#define USBFRNUM 6
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#define USBFLBASEADD 8
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#define USBSOF 12
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/* USB port status and control registers */
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#define USBPORTSC1 16
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#define USBPORTSC2 18
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#define USBPORTSC_CCS 0x0001 /* Current Connect Status ("device present") */
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#define USBPORTSC_CSC 0x0002 /* Connect Status Change */
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#define USBPORTSC_PE 0x0004 /* Port Enable */
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#define USBPORTSC_PEC 0x0008 /* Port Enable Change */
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#define USBPORTSC_DPLUS 0x0010 /* D+ high (line status) */
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#define USBPORTSC_DMINUS 0x0020 /* D- high (line status) */
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#define USBPORTSC_RD 0x0040 /* Resume Detect */
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#define USBPORTSC_RES1 0x0080 /* reserved, always 1 */
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#define USBPORTSC_LSDA 0x0100 /* Low Speed Device Attached */
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#define USBPORTSC_PR 0x0200 /* Port Reset */
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/* OC and OCC from Intel 430TX and later (not UHCI 1.1d spec) */
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#define USBPORTSC_OC 0x0400 /* Over Current condition */
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#define USBPORTSC_OCC 0x0800 /* Over Current Change R/WC */
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#define USBPORTSC_SUSP 0x1000 /* Suspend */
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#define USBPORTSC_RES2 0x2000 /* reserved, write zeroes */
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#define USBPORTSC_RES3 0x4000 /* reserved, write zeroes */
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#define USBPORTSC_RES4 0x8000 /* reserved, write zeroes */
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/* Legacy support register */
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#define USBLEGSUP 0xc0
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#define USBLEGSUP_DEFAULT 0x2000 /* only PIRQ enable set */
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#define UHCI_NULL_DATA_SIZE 0x7FF /* for UHCI controller TD */
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#define UHCI_PTR_BITS cpu_to_le32(0x000F)
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#define UHCI_PTR_TERM cpu_to_le32(0x0001)
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#define UHCI_PTR_QH cpu_to_le32(0x0002)
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#define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
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#define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
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#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
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#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
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#define CAN_SCHEDULE_FRAMES 1000 /* how far future frames can be scheduled */
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struct uhci_frame_list {
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__le32 frame[UHCI_NUMFRAMES];
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void *frame_cpu[UHCI_NUMFRAMES];
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dma_addr_t dma_handle;
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};
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struct urb_priv;
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/*
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* One role of a QH is to hold a queue of TDs for some endpoint. Each QH is
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* used with one URB, and qh->element (updated by the HC) is either:
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* - the next unprocessed TD for the URB, or
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* - UHCI_PTR_TERM (when there's no more traffic for this endpoint), or
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* - the QH for the next URB queued to the same endpoint.
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*
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* The other role of a QH is to serve as a "skeleton" framelist entry, so we
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* can easily splice a QH for some endpoint into the schedule at the right
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* place. Then qh->element is UHCI_PTR_TERM.
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*
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* In the frame list, qh->link maintains a list of QHs seen by the HC:
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* skel1 --> ep1-qh --> ep2-qh --> ... --> skel2 --> ...
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*/
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struct uhci_qh {
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/* Hardware fields */
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__le32 link; /* Next queue */
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__le32 element; /* Queue element pointer */
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/* Software fields */
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dma_addr_t dma_handle;
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struct usb_device *dev;
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struct urb_priv *urbp;
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struct list_head list; /* P: uhci->frame_list_lock */
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struct list_head remove_list; /* P: uhci->remove_list_lock */
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} __attribute__((aligned(16)));
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/*
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* We need a special accessor for the element pointer because it is
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* subject to asynchronous updates by the controller
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*/
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static __le32 inline qh_element(struct uhci_qh *qh) {
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__le32 element = qh->element;
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barrier();
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return element;
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}
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/*
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* for TD <status>:
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*/
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#define TD_CTRL_SPD (1 << 29) /* Short Packet Detect */
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#define TD_CTRL_C_ERR_MASK (3 << 27) /* Error Counter bits */
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#define TD_CTRL_C_ERR_SHIFT 27
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#define TD_CTRL_LS (1 << 26) /* Low Speed Device */
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#define TD_CTRL_IOS (1 << 25) /* Isochronous Select */
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#define TD_CTRL_IOC (1 << 24) /* Interrupt on Complete */
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#define TD_CTRL_ACTIVE (1 << 23) /* TD Active */
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#define TD_CTRL_STALLED (1 << 22) /* TD Stalled */
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#define TD_CTRL_DBUFERR (1 << 21) /* Data Buffer Error */
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#define TD_CTRL_BABBLE (1 << 20) /* Babble Detected */
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#define TD_CTRL_NAK (1 << 19) /* NAK Received */
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#define TD_CTRL_CRCTIMEO (1 << 18) /* CRC/Time Out Error */
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#define TD_CTRL_BITSTUFF (1 << 17) /* Bit Stuff Error */
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#define TD_CTRL_ACTLEN_MASK 0x7FF /* actual length, encoded as n - 1 */
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#define TD_CTRL_ANY_ERROR (TD_CTRL_STALLED | TD_CTRL_DBUFERR | \
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TD_CTRL_BABBLE | TD_CTRL_CRCTIME | TD_CTRL_BITSTUFF)
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#define uhci_maxerr(err) ((err) << TD_CTRL_C_ERR_SHIFT)
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#define uhci_status_bits(ctrl_sts) ((ctrl_sts) & 0xF60000)
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#define uhci_actual_length(ctrl_sts) (((ctrl_sts) + 1) & TD_CTRL_ACTLEN_MASK) /* 1-based */
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/*
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* for TD <info>: (a.k.a. Token)
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*/
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#define td_token(td) le32_to_cpu((td)->token)
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#define TD_TOKEN_DEVADDR_SHIFT 8
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#define TD_TOKEN_TOGGLE_SHIFT 19
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#define TD_TOKEN_TOGGLE (1 << 19)
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#define TD_TOKEN_EXPLEN_SHIFT 21
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#define TD_TOKEN_EXPLEN_MASK 0x7FF /* expected length, encoded as n - 1 */
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#define TD_TOKEN_PID_MASK 0xFF
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#define uhci_explen(len) ((len) << TD_TOKEN_EXPLEN_SHIFT)
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#define uhci_expected_length(token) ((((token) >> 21) + 1) & TD_TOKEN_EXPLEN_MASK)
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#define uhci_toggle(token) (((token) >> TD_TOKEN_TOGGLE_SHIFT) & 1)
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#define uhci_endpoint(token) (((token) >> 15) & 0xf)
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#define uhci_devaddr(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7f)
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#define uhci_devep(token) (((token) >> TD_TOKEN_DEVADDR_SHIFT) & 0x7ff)
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#define uhci_packetid(token) ((token) & TD_TOKEN_PID_MASK)
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#define uhci_packetout(token) (uhci_packetid(token) != USB_PID_IN)
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#define uhci_packetin(token) (uhci_packetid(token) == USB_PID_IN)
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/*
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* The documentation says "4 words for hardware, 4 words for software".
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*
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* That's silly, the hardware doesn't care. The hardware only cares that
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* the hardware words are 16-byte aligned, and we can have any amount of
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* sw space after the TD entry as far as I can tell.
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*
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* But let's just go with the documentation, at least for 32-bit machines.
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* On 64-bit machines we probably want to take advantage of the fact that
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* hw doesn't really care about the size of the sw-only area.
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*
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* Alas, not anymore, we have more than 4 words for software, woops.
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* Everything still works tho, surprise! -jerdfelt
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*
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* td->link points to either another TD (not necessarily for the same urb or
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* even the same endpoint), or nothing (PTR_TERM), or a QH (for queued urbs)
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*/
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struct uhci_td {
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/* Hardware fields */
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__le32 link;
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__le32 status;
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__le32 token;
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__le32 buffer;
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/* Software fields */
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dma_addr_t dma_handle;
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struct usb_device *dev;
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struct urb *urb;
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struct list_head list; /* P: urb->lock */
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struct list_head remove_list; /* P: uhci->td_remove_list_lock */
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int frame; /* for iso: what frame? */
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struct list_head fl_list; /* P: uhci->frame_list_lock */
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} __attribute__((aligned(16)));
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/*
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* We need a special accessor for the control/status word because it is
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* subject to asynchronous updates by the controller
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*/
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static u32 inline td_status(struct uhci_td *td) {
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__le32 status = td->status;
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barrier();
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return le32_to_cpu(status);
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}
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/*
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* The UHCI driver places Interrupt, Control and Bulk into QH's both
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* to group together TD's for one transfer, and also to faciliate queuing
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* of URB's. To make it easy to insert entries into the schedule, we have
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* a skeleton of QH's for each predefined Interrupt latency, low-speed
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* control, full-speed control and terminating QH (see explanation for
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* the terminating QH below).
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*
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* When we want to add a new QH, we add it to the end of the list for the
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* skeleton QH.
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*
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* For instance, the queue can look like this:
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*
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* skel int128 QH
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* dev 1 interrupt QH
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* dev 5 interrupt QH
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* skel int64 QH
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* skel int32 QH
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* ...
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* skel int1 QH
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* skel low-speed control QH
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* dev 5 control QH
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* skel full-speed control QH
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* skel bulk QH
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* dev 1 bulk QH
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* dev 2 bulk QH
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* skel terminating QH
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*
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* The terminating QH is used for 2 reasons:
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* - To place a terminating TD which is used to workaround a PIIX bug
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* (see Intel errata for explanation)
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* - To loop back to the full-speed control queue for full-speed bandwidth
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* reclamation
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*
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* Isochronous transfers are stored before the start of the skeleton
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* schedule and don't use QH's. While the UHCI spec doesn't forbid the
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* use of QH's for Isochronous, it doesn't use them either. Since we don't
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* need to use them either, we follow the spec diagrams in hope that it'll
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* be more compatible with future UHCI implementations.
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*/
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#define UHCI_NUM_SKELQH 12
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#define skel_int128_qh skelqh[0]
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#define skel_int64_qh skelqh[1]
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#define skel_int32_qh skelqh[2]
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#define skel_int16_qh skelqh[3]
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#define skel_int8_qh skelqh[4]
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#define skel_int4_qh skelqh[5]
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#define skel_int2_qh skelqh[6]
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#define skel_int1_qh skelqh[7]
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#define skel_ls_control_qh skelqh[8]
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#define skel_fs_control_qh skelqh[9]
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#define skel_bulk_qh skelqh[10]
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#define skel_term_qh skelqh[11]
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/*
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* Search tree for determining where <interval> fits in the skelqh[]
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* skeleton.
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*
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* An interrupt request should be placed into the slowest skelqh[]
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* which meets the interval/period/frequency requirement.
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* An interrupt request is allowed to be faster than <interval> but not slower.
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*
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* For a given <interval>, this function returns the appropriate/matching
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* skelqh[] index value.
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*/
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static inline int __interval_to_skel(int interval)
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{
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if (interval < 16) {
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if (interval < 4) {
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if (interval < 2)
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return 7; /* int1 for 0-1 ms */
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return 6; /* int2 for 2-3 ms */
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}
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if (interval < 8)
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return 5; /* int4 for 4-7 ms */
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return 4; /* int8 for 8-15 ms */
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}
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if (interval < 64) {
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if (interval < 32)
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return 3; /* int16 for 16-31 ms */
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return 2; /* int32 for 32-63 ms */
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}
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if (interval < 128)
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return 1; /* int64 for 64-127 ms */
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return 0; /* int128 for 128-255 ms (Max.) */
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}
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/*
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* Device states for the host controller.
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*
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* To prevent "bouncing" in the presence of electrical noise,
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* we insist on a 1-second "grace" period, before switching to
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* the RUNNING or SUSPENDED states, during which the state is
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* not allowed to change.
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*
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* The resume process is divided into substates in order to avoid
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* potentially length delays during the timer handler.
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*
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* States in which the host controller is halted must have values <= 0.
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*/
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enum uhci_state {
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UHCI_RESET,
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UHCI_RUNNING_GRACE, /* Before RUNNING */
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UHCI_RUNNING, /* The normal state */
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UHCI_SUSPENDING_GRACE, /* Before SUSPENDED */
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UHCI_SUSPENDED = -10, /* When no devices are attached */
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UHCI_RESUMING_1,
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UHCI_RESUMING_2
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};
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/*
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* This describes the full uhci information.
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*
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* Note how the "proper" USB information is just
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* a subset of what the full implementation needs.
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*/
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struct uhci_hcd {
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/* debugfs */
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struct dentry *dentry;
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/* Grabbed from PCI */
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unsigned long io_addr;
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struct dma_pool *qh_pool;
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struct dma_pool *td_pool;
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struct usb_bus *bus;
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struct uhci_td *term_td; /* Terminating TD, see UHCI bug */
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struct uhci_qh *skelqh[UHCI_NUM_SKELQH]; /* Skeleton QH's */
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spinlock_t lock;
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struct uhci_frame_list *fl; /* P: uhci->lock */
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int fsbr; /* Full-speed bandwidth reclamation */
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unsigned long fsbrtimeout; /* FSBR delay */
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enum uhci_state state; /* FIXME: needs a spinlock */
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unsigned long state_end; /* Time of next transition */
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unsigned int frame_number; /* As of last check */
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unsigned int is_stopped;
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#define UHCI_IS_STOPPED 9999 /* Larger than a frame # */
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unsigned int scan_in_progress:1; /* Schedule scan is running */
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unsigned int need_rescan:1; /* Redo the schedule scan */
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unsigned int resume_detect:1; /* Need a Global Resume */
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/* Support for port suspend/resume/reset */
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unsigned long port_c_suspend; /* Bit-arrays of ports */
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unsigned long suspended_ports;
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unsigned long resuming_ports;
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unsigned long ports_timeout; /* Time to stop signalling */
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/* Main list of URB's currently controlled by this HC */
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struct list_head urb_list; /* P: uhci->lock */
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/* List of QH's that are done, but waiting to be unlinked (race) */
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struct list_head qh_remove_list; /* P: uhci->lock */
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unsigned int qh_remove_age; /* Age in frames */
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/* List of TD's that are done, but waiting to be freed (race) */
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struct list_head td_remove_list; /* P: uhci->lock */
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unsigned int td_remove_age; /* Age in frames */
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/* List of asynchronously unlinked URB's */
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struct list_head urb_remove_list; /* P: uhci->lock */
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unsigned int urb_remove_age; /* Age in frames */
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/* List of URB's awaiting completion callback */
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struct list_head complete_list; /* P: uhci->lock */
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int rh_numports;
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struct timer_list stall_timer;
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wait_queue_head_t waitqh; /* endpoint_disable waiters */
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};
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/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
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static inline struct uhci_hcd *hcd_to_uhci(struct usb_hcd *hcd)
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{
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return (struct uhci_hcd *) (hcd->hcd_priv);
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}
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static inline struct usb_hcd *uhci_to_hcd(struct uhci_hcd *uhci)
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{
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return container_of((void *) uhci, struct usb_hcd, hcd_priv);
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}
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#define uhci_dev(u) (uhci_to_hcd(u)->self.controller)
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struct urb_priv {
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struct list_head urb_list;
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struct urb *urb;
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struct uhci_qh *qh; /* QH for this URB */
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struct list_head td_list; /* P: urb->lock */
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unsigned fsbr : 1; /* URB turned on FSBR */
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unsigned fsbr_timeout : 1; /* URB timed out on FSBR */
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unsigned queued : 1; /* QH was queued (not linked in) */
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unsigned short_control_packet : 1; /* If we get a short packet during */
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/* a control transfer, retrigger */
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/* the status phase */
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unsigned long inserttime; /* In jiffies */
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unsigned long fsbrtime; /* In jiffies */
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struct list_head queue_list; /* P: uhci->frame_list_lock */
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};
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/*
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* Locking in uhci.c
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*
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* Almost everything relating to the hardware schedule and processing
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* of URBs is protected by uhci->lock. urb->status is protected by
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* urb->lock; that's the one exception.
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*
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* To prevent deadlocks, never lock uhci->lock while holding urb->lock.
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* The safe order of locking is:
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*
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* #1 uhci->lock
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* #2 urb->lock
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*/
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#endif
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