368dd5acd1
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/* MN10300 On-board interrupt controller registers
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*
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* Copyright (C) 2007 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public Licence
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* as published by the Free Software Foundation; either version
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* 2 of the Licence, or (at your option) any later version.
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*/
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#ifndef _ASM_INTCTL_REGS_H
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#define _ASM_INTCTL_REGS_H
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#include <asm/cpu-regs.h>
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#ifdef __KERNEL__
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/*
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* Interrupt controller registers
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* - Registers 64-191 are at addresses offset from the main array
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*/
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#define GxICR(X) \
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__SYSREG(0xd4000000 + (X) * 4 + \
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(((X) >= 64) && ((X) < 192)) * 0xf00, u16)
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#define GxICR_u8(X) \
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__SYSREG(0xd4000000 + (X) * 4 + \
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(((X) >= 64) && ((X) < 192)) * 0xf00, u8)
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#include <proc/intctl-regs.h>
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#define XIRQ_TRIGGER_LOWLEVEL 0
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#define XIRQ_TRIGGER_HILEVEL 1
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#define XIRQ_TRIGGER_NEGEDGE 2
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#define XIRQ_TRIGGER_POSEDGE 3
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/* non-maskable interrupt control */
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#define NMIIRQ 0
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#define NMICR GxICR(NMIIRQ) /* NMI control register */
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#define NMICR_NMIF 0x0001 /* NMI pin interrupt flag */
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#define NMICR_WDIF 0x0002 /* watchdog timer overflow flag */
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#define NMICR_ABUSERR 0x0008 /* async bus error flag */
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/* maskable interrupt control */
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#define GxICR_DETECT 0x0001 /* interrupt detect flag */
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#define GxICR_REQUEST 0x0010 /* interrupt request flag */
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#define GxICR_ENABLE 0x0100 /* interrupt enable flag */
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#define GxICR_LEVEL 0x7000 /* interrupt priority level */
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#define GxICR_LEVEL_0 0x0000 /* - level 0 */
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#define GxICR_LEVEL_1 0x1000 /* - level 1 */
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#define GxICR_LEVEL_2 0x2000 /* - level 2 */
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#define GxICR_LEVEL_3 0x3000 /* - level 3 */
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#define GxICR_LEVEL_4 0x4000 /* - level 4 */
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#define GxICR_LEVEL_5 0x5000 /* - level 5 */
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#define GxICR_LEVEL_6 0x6000 /* - level 6 */
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#define GxICR_LEVEL_SHIFT 12
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#define GxICR_NMI 0x8000 /* nmi request flag */
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#define NUM2GxICR_LEVEL(num) ((num) << GxICR_LEVEL_SHIFT)
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#ifndef __ASSEMBLY__
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extern void set_intr_level(int irq, u16 level);
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extern void mn10300_intc_set_level(unsigned int irq, unsigned int level);
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extern void mn10300_intc_clear(unsigned int irq);
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extern void mn10300_intc_set(unsigned int irq);
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extern void mn10300_intc_enable(unsigned int irq);
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extern void mn10300_intc_disable(unsigned int irq);
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extern void mn10300_set_lateack_irq_type(int irq);
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#endif
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/* external interrupts */
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#define XIRQxICR(X) GxICR((X)) /* external interrupt control regs */
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#endif /* __KERNEL__ */
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#endif /* _ASM_INTCTL_REGS_H */
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