8f4a9e525a
C290PCIe has NAND flash present on IFC Chip Select(CS) 1. So Add "ranges" field for NAND flash on CS1. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
225 lines
5.3 KiB
Plaintext
225 lines
5.3 KiB
Plaintext
/*
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* C293 PCIE Device Tree Source
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*
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* Copyright 2013 Freescale Semiconductor Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of Freescale Semiconductor nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") as published by the Free Software
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* Foundation, either version 2 of that License or (at your option) any
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* later version.
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*
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* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
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* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/include/ "fsl/c293si-pre.dtsi"
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/ {
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model = "fsl,C293PCIE";
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compatible = "fsl,C293PCIE";
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memory {
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device_type = "memory";
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};
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ifc: ifc@fffe1e000 {
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reg = <0xf 0xffe1e000 0 0x2000>;
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ranges = <0x0 0x0 0xf 0xec000000 0x04000000
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0x1 0x0 0xf 0xff800000 0x00010000
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0x2 0x0 0xf 0xffdf0000 0x00010000>;
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};
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soc: soc@fffe00000 {
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ranges = <0x0 0xf 0xffe00000 0x100000>;
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};
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pci0: pcie@fffe0a000 {
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reg = <0xf 0xffe0a000 0 0x1000>;
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ranges = <0x2000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000
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0x1000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x10000>;
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pcie@0 {
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ranges = <0x2000000 0x0 0x80000000
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0x2000000 0x0 0x80000000
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0x0 0x20000000
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0x1000000 0x0 0x0
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0x1000000 0x0 0x0
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0x0 0x100000>;
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};
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};
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};
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&ifc {
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nor@0,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "cfi-flash";
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reg = <0x0 0x0 0x4000000>;
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bank-width = <2>;
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device-width = <1>;
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partition@0 {
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/* 1MB for DTB Image */
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reg = <0x0 0x00100000>;
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label = "NOR DTB Image";
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};
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partition@100000 {
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/* 8 MB for Linux Kernel Image */
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reg = <0x00100000 0x00800000>;
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label = "NOR Linux Kernel Image";
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};
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partition@900000 {
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/* 53MB for rootfs */
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reg = <0x00900000 0x03500000>;
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label = "NOR Rootfs Image";
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};
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partition@3e00000 {
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/* 1MB for blob encrypted key */
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reg = <0x03e00000 0x00100000>;
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label = "NOR blob encrypted key";
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};
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partition@3f00000 {
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/* 512KB for u-boot Bootloader Image and evn */
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reg = <0x03f00000 0x00100000>;
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label = "NOR U-Boot Image";
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read-only;
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};
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};
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nand@1,0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "fsl,ifc-nand";
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reg = <0x1 0x0 0x10000>;
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partition@0 {
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/* This location must not be altered */
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/* 1MB for u-boot Bootloader Image */
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reg = <0x0 0x00100000>;
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label = "NAND U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 1MB for DTB Image */
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reg = <0x00100000 0x00100000>;
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label = "NAND DTB Image";
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};
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partition@200000 {
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/* 16MB for Linux Kernel Image */
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reg = <0x00200000 0x01000000>;
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label = "NAND Linux Kernel Image";
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};
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partition@1200000 {
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/* 4078MB for Root file System Image */
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reg = <0x00600000 0xfee00000>;
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label = "NAND RFS Image";
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};
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};
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cpld@2,0 {
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compatible = "fsl,c293pcie-cpld";
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reg = <0x2 0x0 0x20>;
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};
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};
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&soc {
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i2c@3000 {
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eeprom@50 {
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compatible = "st,24c1024";
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reg = <0x50>;
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};
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adt7461@4c {
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compatible = "adi,adt7461";
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reg = <0x4c>;
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};
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};
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spi@7000 {
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flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "spansion,s25sl12801";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partition@0 {
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/* 1MB for u-boot Bootloader Image */
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/* 1MB for Environment */
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reg = <0x0 0x00100000>;
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label = "SPI Flash U-Boot Image";
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read-only;
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};
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partition@100000 {
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/* 512KB for DTB Image */
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reg = <0x00100000 0x00080000>;
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label = "SPI Flash DTB Image";
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};
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partition@180000 {
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/* 4MB for Linux Kernel Image */
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reg = <0x00180000 0x00400000>;
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label = "SPI Flash Linux Kernel Image";
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};
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partition@580000 {
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/* 10.5MB for RFS Image */
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reg = <0x00580000 0x00a80000>;
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label = "SPI Flash RFS Image";
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};
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};
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};
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mdio@24000 {
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phy0: ethernet-phy@0 {
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interrupts = <2 1 0 0>;
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reg = <0x0>;
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};
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phy1: ethernet-phy@1 {
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interrupts = <2 1 0 0>;
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reg = <0x2>;
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};
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};
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enet0: ethernet@b0000 {
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phy-handle = <&phy0>;
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phy-connection-type = "rgmii-id";
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};
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enet1: ethernet@b1000 {
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phy-handle = <&phy1>;
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phy-connection-type = "rgmii-id";
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};
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};
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/include/ "fsl/c293si-post.dtsi"
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